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Custom IC Design Forum

Page 135 of 157     First ... 131132133134135136137138139 ... Last
  Topics   Replies     Views     Last Post  
Post Any body plz help me for transformer stimulation in pspice.
started by jogy  on 16 Sep 2009 12:50 AM   
0 950 By jogy
16 Sep 2009 12:50 AM   
Post parasitic bjt layout (latteral)
started by depp  on 15 Sep 2009 11:42 PM   
0 1373 By depp
15 Sep 2009 11:42 PM   
Post Cadence 5. Trouble with simualting basic element in project.
started by StreamCX  on 15 Sep 2009 03:43 AM   
1 680 By Andrew Beckett
15 Sep 2009 04:19 AM   
Post ams: simulating design with spice netlist with bus ports
started by Runner  on 14 Sep 2009 05:02 AM   
1 2110 By Andrew Beckett
14 Sep 2009 05:07 AM   
Post ruler in virtuoso Layout L - problem solved
started by vikaspadu  on 11 Sep 2009 06:59 PM   
2 2323 By vikaspadu
11 Sep 2009 09:24 PM   
Post ADE(GUI) DC analysis query
started by eppramod  on 09 Sep 2009 10:01 AM   
3 1053 By eppramod
10 Sep 2009 01:33 AM   
Post Encounter "short" violations
started by superman321  on 08 Sep 2009 07:11 PM   
2 861 By Andrew Beckett
09 Sep 2009 10:28 AM   
Post How to get min value of a transistor width/length in a given pdk by skill?
started by IC Layout  on 08 Sep 2009 08:00 AM   
1 2252 By Andrew Beckett
08 Sep 2009 08:37 AM   
Post Can OpenAccess stream in abd out gzip gds
started by Bidou  on 04 Sep 2009 11:04 AM   
1 751 By Andrew Beckett
07 Sep 2009 01:39 AM   
Post Layout and LVS of a non-standard device!
started by Ueue  on 03 Sep 2009 01:03 AM   
3 1316 By Andrew Beckett
03 Sep 2009 02:41 PM   
Post Cut Guard Ring - TTB
started by kashvi  on 03 Sep 2009 01:49 AM   
0 786 By kashvi
03 Sep 2009 01:49 AM   
Post Questions Regarding the Virtuoso XL Layout
started by tester  on 29 Aug 2009 04:48 PM   
3 911 By Vabzter
02 Sep 2009 02:35 AM   
Post MOS area and perimeter are not calculated from parametrized w and l
started by joliveros  on 09 Jun 2009 09:57 PM   
3 2144 By Andrew Beckett
02 Sep 2009 12:30 AM   
Post Cannot view output log in ADE GXL during simulation
started by Grover  on 01 Sep 2009 01:40 AM   
6 2277 By Grover
01 Sep 2009 03:47 AM   
Post behavioral VHDL description to Cadence Schematic
started by PrachiB  on 27 Aug 2009 08:45 AM   
2 1619 By Andrew Beckett
01 Sep 2009 02:30 AM   
Post hexadecimal numbers in veriloga
started by Nikolaj  on 01 Sep 2009 01:11 AM   
3 1517 By Andrew Beckett
01 Sep 2009 01:38 AM   
Post executable ncsim is not found in UNIX path
started by PrachiB  on 28 Aug 2009 04:53 PM   
2 1387 By PrachiB
31 Aug 2009 05:35 PM   
Post IUS8.2: convert logic value to wreal
started by Chris Smit  on 28 Aug 2009 05:12 AM   
1 1088 By Chris Smit
28 Aug 2009 06:35 AM   
Post Assert checks for overvoltage with duty-cycle
started by MarkSummers  on 18 Aug 2009 07:44 AM   
7 2489 By MarkSummers
26 Aug 2009 09:50 AM   
Post Monte Carlo simulation
started by whlinfei  on 20 Aug 2009 12:10 AM   
3 2791 By Andrew Beckett
26 Aug 2009 02:57 AM   

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