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Custom IC Design Forum

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Post ADE plot outputs Cadence5
started by StreamCX  on 13 Jun 2010 12:53 PM   
1 1149 By Quek
26 Jun 2010 06:34 PM   
Post ASSURA LVS PROBLEM FOR AMI C5 PDK
started by CHECKMATE  on 21 Jun 2010 04:18 PM   
6 2596 By CHECKMATE
24 Jun 2010 11:38 AM   
Post Cadence 5: Change path width with bindkey
started by frogconsultant  on 22 Jun 2010 09:08 AM   
2 1484 By frogconsultant
23 Jun 2010 07:06 AM   
Post HD2 and HD3 vs Frequency plot
started by Verdhan  on 23 Jun 2010 03:39 AM   
0 1516 By Verdhan
23 Jun 2010 03:39 AM   
Post Some DRC errors regarding pwell
started by tester  on 19 Jun 2010 01:15 AM   
3 1073 By Quek
20 Jun 2010 04:58 PM   
Post convert schematics or simulation results to PDF
started by tyanata  on 01 Jun 2010 11:54 PM   
14 6336 By tyanata
17 Jun 2010 11:28 PM   
Post Problems with expressions in Monte Carlo
started by Karo  on 14 Jun 2010 10:45 PM   
6 1664 By Karo
17 Jun 2010 08:12 AM   
Post Check in Spectre license automatically
started by AnalogGR  on 15 Jun 2010 07:13 AM   
2 1723 By AnalogGR
16 Jun 2010 04:34 AM   
Post how to run the simulaiton for 1 ns step interval ..?
started by Sunil Kumar K  on 31 May 2010 12:27 AM   
5 1350 By Sunil Kumar K
16 Jun 2010 02:32 AM   
Post Text output on Cadence Composer
started by Vijay095  on 24 May 2010 10:22 AM   
4 1825 By Andrew Beckett
16 Jun 2010 02:32 AM   
Post creating a matrix of instances in verilog-A
started by rickrevolta  on 20 May 2010 05:28 AM   
2 3209 By Andrew Beckett
16 Jun 2010 02:32 AM   
Post Pin names
started by StreamCX  on 20 May 2010 05:41 AM   
7 2296 By Andrew Beckett
16 Jun 2010 02:32 AM   
Post LvsIgnore Properties
started by frogconsultant  on 08 Mar 2010 03:22 PM   
12 7982 By frogconsultant
16 Jun 2010 02:32 AM   
Post How to implement this equation in VerilogA
started by princemahmmod  on 20 Apr 2010 06:00 AM   
4 2085 By Andrew Beckett
16 Jun 2010 02:32 AM   
Post Cadence 6 waveform error vpwl vsrc
started by StreamCX  on 11 Jun 2010 08:27 AM   
9 3136 By StreamCX
16 Jun 2010 02:06 AM   
Post Ruler setup
started by tester  on 04 Jun 2010 09:04 AM   
8 2403 By tester
16 Jun 2010 12:41 AM   
Post Output SPEF-file from QRC contains only top level ports
started by Slawa  on 07 Jun 2010 07:38 AM   
1 1125 By Quek
12 Jun 2010 09:49 PM   
Post How to get a free student copy of NC Verilog Simulator
started by laddu0  on 25 Apr 2010 07:14 AM   
5 4950 By Quek
12 Jun 2010 02:30 AM   
Post Off-Grid pins warning in abstract generation
started by affaq  on 09 Jun 2010 01:56 AM   
3 997 By Alex Soyer
09 Jun 2010 04:09 AM   
Post subciruit initiated top-level current probe
started by Kalimero  on 07 Jun 2010 02:37 AM   
5 1840 By Kalimero
08 Jun 2010 10:25 PM   

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