Home > Community > Forums > Custom IC Design

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Custom IC Design Forum

Page 116 of 147     First ... 112113114115116117118119120 ... Last
  Topics   Replies     Views     Last Post  
Post Using spectre netlist as input to ASSURA
started by yoyega  on 12 Oct 2009 07:15 AM   
6 2439 By yoyega
06 Mar 2010 09:24 PM   
Post how to speed up transient analysis?
started by minci  on 05 Mar 2010 03:22 PM   
1 1932 By Quek
06 Mar 2010 05:22 AM   
Post Disappearing geometry
started by Dean1138  on 04 Mar 2010 05:34 PM   
2 1017 By Dean1138
05 Mar 2010 05:11 PM   
Post How to probe in av_extracted view?
started by starsky  on 27 Feb 2010 09:54 AM   
8 3839 By Andrew Beckett
05 Mar 2010 01:32 PM   
Post CMX Error
started by tswong  on 03 Mar 2010 12:04 PM   
3 1262 By Quek
05 Mar 2010 05:03 AM   
Post Spacing for IO pins
started by tswong  on 03 Mar 2010 12:10 PM   
5 1106 By Alex Soyer
04 Mar 2010 12:01 PM   
Post Knowing rerun number...
started by Larry Allen  on 02 Mar 2010 07:51 PM   
1 694 By skillUser
02 Mar 2010 10:34 PM   
Post multithread ams simulation
started by Raullsitec  on 19 Feb 2010 11:01 PM   
1 1250 By Ramkumar M
02 Mar 2010 08:39 PM   
Post Using Print in Spectre
started by TimCoyle  on 25 Feb 2010 11:17 PM   
5 3113 By TimCoyle
02 Mar 2010 05:51 PM   
Post Unable to descend into verilogA view
started by Ramya Deepika  on 01 Mar 2010 11:35 AM   
1 1068 By skillUser
01 Mar 2010 08:11 PM   
Post autodraw option
started by arpi  on 28 Feb 2010 02:39 AM   
1 927 By Quek
28 Feb 2010 05:00 AM   
Post How to suppress Spectre simulation for digital design?
started by Shengkui Gao  on 25 Feb 2010 10:13 PM   
3 2331 By Quek
27 Feb 2010 04:56 AM   
Post How to make modgen always treat parallel transistors as m-factor
started by Grover  on 24 Feb 2010 05:51 PM   
5 2306 By Quek
26 Feb 2010 04:40 PM   
Post Connecting dummy transistors
started by Grover  on 24 Feb 2010 07:16 PM   
3 1660 By Quek
26 Feb 2010 04:23 PM   
Post Cadence IC6 How to Get all the data graph
started by Yousuf  on 19 Feb 2010 12:49 AM   
2 1349 By Yousuf
26 Feb 2010 01:45 PM   
Post descend in schematic
started by The Consultant  on 18 Feb 2010 07:43 PM   
5 2361 By Andrew Beckett
25 Feb 2010 04:16 PM   
Post how to copy a cellview from a different cell
started by kristin  on 21 Feb 2010 08:11 AM   
3 2304 By Andrew Beckett
23 Feb 2010 01:00 AM   
Post Including PWL files in Spectre
started by kumarp  on 18 Feb 2010 10:09 AM   
2 2802 By kumarp
21 Feb 2010 04:46 AM   
Post Saving verilog-A variables in UltraSim
started by TonySal  on 20 Feb 2010 05:46 AM   
1 1428 By Quek
20 Feb 2010 08:17 AM   
Post Cadence to Hierarchical PDF
started by Drwinco  on 19 Feb 2010 07:45 AM   
3 2236 By dmay
19 Feb 2010 09:49 PM   

Page 116 of 147     First ... 112113114115116117118119120 ... Last

There are 282 guest(s) and 2 member(s) online:
Tom Volden, stacyw

Most Active Users


Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.