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Custom IC Design Forum

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  Topics   Replies     Views     Last Post  
Sticky Guidelines for the Custom IC Design Forum
started by Andrew Beckett  on 29 Jul 2011 01:20 AM    		0 9628 By Andrew Beckett
29 Jul 2011 01:20 AM   
Post Connectivity->Update->Layout Parameters problem
started by pham777  on 06 May 2013 11:13 AM    		9 135 By pham777
Yesterday at 01:30 PM   
Post OCEAN write generic procedure to plot waveforms
started by The Setlaz  on 13 May 2013 08:48 AM    		6 82 By The Setlaz
Yesterday at 07:36 AM   
Post Problem simulating Spice Netlist with Spectre
started by Oriba  on 10 Apr 2013 12:38 AM    		7 230 By Andrew Beckett
Yesterday at 06:19 AM   
Post Noise sources in PSS analysis
started by OneNewBoy  on 14 May 2013 05:51 PM    		1 44 By Andrew Beckett
Yesterday at 04:43 AM   
Post Relative include path for a vpwlf source
started by TonySal  on 16 May 2013 01:24 PM    		1 30 By Andrew Beckett
Yesterday at 01:41 AM   
Post ADE XL annotation affects schematic hierarchy
started by Rowlf  on 14 May 2013 02:50 AM    		2 46 By Rowlf
Yesterday at 01:11 AM   
Post ASCII waveform file format for Virtuoso Visualization and Analysis XL?
started by Andy Stewart  on 14 May 2013 08:35 AM    		2 72 By Andrew Beckett
16 May 2013 01:05 AM   
Post Personal license
started by jsums  on 15 May 2013 06:21 AM    		1 41 By Andrew Beckett
16 May 2013 01:01 AM   
Post Post-processing non-PSF results formats through OCEAN
started by mnabil  on 14 May 2013 12:17 PM    		3 53 By Andrew Beckett
16 May 2013 12:58 AM   
Post Error in VerilogA : neither a branch nor a net name
started by sreeni  on 15 May 2013 02:02 AM    		1 35 By Andrew Beckett
15 May 2013 03:26 AM   
Post Changing layer numbers in a design library
started by Lynks  on 14 May 2013 02:03 PM    		0 38 By Lynks
14 May 2013 02:03 PM   
Post verilog simulation
started by apple419  on 12 May 2013 06:34 PM    		5 72 By Andrew Beckett
13 May 2013 09:09 AM   
Post Netlisting fine, but simulation fails: *Error* eval: unbound variable - currentFormSave
started by tito80  on 10 May 2013 05:27 PM    		1 69 By Andrew Beckett
13 May 2013 03:46 AM   
Post Error invoking virtuoso IC615
started by emax  on 09 May 2013 08:46 AM    		1 69 By theopaone
09 May 2013 08:51 AM   
Post check the instance symbol change in schematic
started by lzyc  on 08 May 2013 03:55 PM    		3 71 By theopaone
09 May 2013 08:45 AM   
Post Need to place a pin on the symbol for an internal VerilogA signal
started by boast  on 07 May 2013 04:01 PM    		2 136 By boast
08 May 2013 08:59 AM   
Post CDB to OA Conversion: Layout Issue
started by sebastion  on 30 Apr 2013 03:33 PM    		11 197 By Andrew Beckett
08 May 2013 06:24 AM   
Post Regarding stability sims (STB) --> Over corners STB phase plots shows reversal
started by kasj  on 06 May 2013 05:02 PM    		2 80 By kasj
07 May 2013 07:45 AM   
Post Generating .lib file from layout
started by govilv  on 22 Jun 2009 12:25 PM    		3 1766 By mariek
07 May 2013 05:30 AM   

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