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Custom IC Design Forum

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Sticky Guidelines for the Custom IC Design Forum
started by Andrew Beckett  on 29 Jul 2011 01:20 AM   
0 19994 By Andrew Beckett
29 Jul 2011 01:20 AM   
Post cdb2oa (PcellEvalFail)
started by Peter123  on 22 May 2012 01:15 AM   
3 1290 By Prasanna7
Today at 03:09 AM   
Post Zero Diagonal Matrix in Jacobian on Net-x
started by RFStuff  on Yesterday at 11:31 PM   
0 17 By RFStuff
Yesterday at 11:31 PM   
Post VerilogA compiler
started by Sali  on 04 Jul 2014 10:54 AM   
8 442 By Sali
Yesterday at 12:50 PM   
Post Generating ocean script in Linux terminal.
started by RFStuff  on 30 Jun 2014 11:28 PM   
3 434 By skillUser
Yesterday at 10:34 AM   
Post parametric analysis of mosfet length and width
started by madhanmo  on Yesterday at 09:49 AM   
0 33 By madhanmo
Yesterday at 09:49 AM   
Post Memory instance : ULTRASIM simulator setting
started by samung  on Yesterday at 07:07 AM   
0 31 By samung
Yesterday at 07:07 AM   
Post From spectremdl to ultrasim : any cadence solution ?
started by samung  on 24 Jul 2014 08:03 AM   
6 42 By Andrew Beckett
Yesterday at 07:06 AM   
Post ADEXL parametric sweep does not work
started by sram8t  on 10 Jul 2014 04:59 AM   
1 183 By Andrew Beckett
Yesterday at 02:47 AM   
Post Regarding : PVS - QRC RUN FAILURE
started by narendra046  on 14 Jul 2014 11:27 PM   
3 61 By Andrew Beckett
Yesterday at 02:33 AM   
Post Extracted parameters do not match with the schematic.
started by jagadishdn  on 15 Jul 2014 10:34 PM   
2 31 By jagadishdn
29 Jul 2014 10:01 PM   
Post how to save transient data with arbitrary step size?
started by VahidDR  on 29 Jul 2014 10:51 AM   
1 29 By Andrew Beckett
29 Jul 2014 12:58 PM   
Post How to multiply a waveform with the x axis vector
started by milind0y  on 25 Jul 2014 01:39 PM   
2 29 By milind0y
29 Jul 2014 10:52 AM   
Post Layout Porting between Foundries
started by KKANDOTH  on 23 Jul 2014 06:54 AM   
5 25 By theopaone
29 Jul 2014 10:05 AM   
Post Link pin labels over hierarchy
started by Narasimhan90  on 28 Jul 2014 11:15 AM   
3 23 By Andrew Beckett
29 Jul 2014 09:59 AM   
Post Knowing associated TECH-FILE location
started by RFStuff  on 14 Jul 2014 01:59 PM   
3 73 By Andrew Beckett
29 Jul 2014 07:32 AM   
Post Entering infoname and info (captab) analysis in ADE
started by RFStuff  on 29 Jul 2014 02:53 AM   
3 20 By Andrew Beckett
29 Jul 2014 04:04 AM   
Post Processing cadence result data from psf folder
started by RFStuff  on 11 Jul 2014 06:01 AM   
7 190 By Andrew Beckett
29 Jul 2014 02:49 AM   
Post NC-Verilog netlister setttings to output single netlist (not hierarchy-ihnl/ based)
started by jagarcia85  on 09 Apr 2011 03:45 AM   
3 1331 By Andrew Beckett
29 Jul 2014 02:35 AM   
Post Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)
started by RFStuff  on 27 Jun 2014 10:28 AM   
1 499 By Andrew Beckett
29 Jul 2014 01:50 AM   

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