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Custom IC Design Forum

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Sticky Guidelines for the Custom IC Design Forum
started by Andrew Beckett  on 29 Jul 2011 01:20 AM   
0 19901 By Andrew Beckett
29 Jul 2011 01:20 AM   
Post OCEAN SCRIPT for getting dynamic energy consumption
started by Carmichaeli  on Today at 07:19 PM   
0 17 By Carmichaeli
Today at 07:19 PM   
Post SPEF file comparison for Calibre xRC and StarRC
started by frasheed  on Yesterday at 04:41 PM   
2 69 By frasheed
Today at 06:44 AM   
Post CAPTAB DETAILS
started by auto dipper  on 07 Jul 2014 04:56 PM   
6 302 By auto dipper
Today at 06:42 AM   
Post Bind key to change Path end type(ex:extend,truncate,round,variable)
started by KarthikJaiho  on 09 Jul 2014 04:15 AM   
2 145 By KarthikJaiho
Today at 02:31 AM   
Post VerilogA compiler
started by Sali  on 04 Jul 2014 10:54 AM   
5 307 By Andrew Beckett
Today at 01:17 AM   
Post Processing cadence result data from psf folder
started by RFStuff  on Yesterday at 06:01 AM   
5 91 By smlogan
Yesterday at 09:56 AM   
Post RVE CN command equivalent to PVS
started by jorenrefuerzo  on Yesterday at 12:26 AM   
1 84 By Andrew Beckett
Yesterday at 05:38 AM   
Post Importing .gds file in virtuoso
started by RFStuff  on 09 Jul 2014 09:05 AM   
2 133 By RFStuff
Yesterday at 05:27 AM   
Post How to create layout xl for user defined pcell with same parameters as in schematic??
started by KarthikJaiho  on 09 Jul 2014 09:51 PM   
1 116 By Andrew Beckett
Yesterday at 02:18 AM   
Post Abstract Generator : 2 layouts of a same "Memory instance" identified as "Block" and "Core" why ?
started by samung  on 10 Jul 2014 09:23 AM   
1 103 By ColinSutlieff
Yesterday at 12:42 AM   
Post ADEXL parametric sweep does not work
started by sram8t  on 10 Jul 2014 04:59 AM   
0 94 By sram8t
10 Jul 2014 04:59 AM   
Post Netlist error when simulating BSIMCMG
started by Chen23  on 09 Jul 2014 07:18 AM   
1 129 By Chen23
09 Jul 2014 08:26 AM   
Post Specify a file path as a parameter type in Cadence VerilogAMS
started by uzzy  on 02 Oct 2012 07:52 PM   
3 1309 By StephenB
08 Jul 2014 01:19 PM   
Post Cant find PTAP contact in TSMC 0.18u deep technology (NCSU_TechLib_tsmc02d)
started by rajrevanth61  on 08 Jul 2014 12:24 PM   
0 134 By rajrevanth61
08 Jul 2014 12:24 PM   
Post ABSTRACT GENERATOR : absSelectCell for a multi-cells Library, syntax ?
started by samung  on 08 Jul 2014 03:14 AM   
2 193 By samung
08 Jul 2014 08:09 AM   
Post APS:Command line: Multi-Processing
started by Ionutz  on 08 Jul 2014 03:00 AM   
0 177 By Ionutz
08 Jul 2014 03:00 AM   
Post Design rules for library TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block)
started by rajrevanth61  on 07 Jul 2014 10:04 AM   
1 171 By ColinSutlieff
08 Jul 2014 12:39 AM   
Post connect all the bus lines together
started by Clidre  on 07 Jul 2014 09:23 AM   
3 180 By smlogan
07 Jul 2014 12:00 PM   
Post Convergence problem in MC simulations
started by Flyyn Rider  on 07 Jul 2014 06:59 AM   
1 167 By Andrew Beckett
07 Jul 2014 07:02 AM   

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