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Logic Design Forum

Page 9 of 28     First ... 5678910111213 ... Last
  Topics   Replies     Views     Last Post  
Post Best flow to map most key points before compare
started by AntonioL  on 28 Mar 2012 02:24 AM   
2 2866 By AntonioL
29 Mar 2012 11:50 PM   
Post RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement
started by mamsadegh  on 29 Mar 2012 02:37 AM   
0 2487 By mamsadegh
29 Mar 2012 02:37 AM   
Post RTL Compiler - "synthesize -to_generic" generated verilog netlist has delay!
started by mamsadegh  on 29 Mar 2012 02:27 AM   
0 2429 By mamsadegh
29 Mar 2012 02:27 AM   
Post RTL Compiler -- clock latency
started by amitram  on 17 Mar 2012 01:31 PM   
1 2451 By grasshopper
28 Mar 2012 06:10 AM   
Post I am using FreePDK45nm library. I couldn't synthesise a register file.
started by Thommandram  on 21 Mar 2012 10:01 AM   
1 2139 By grasshopper
28 Mar 2012 06:07 AM   
Post Procedure to define a new VHDL library in RTL compiler script
started by shustar  on 26 Mar 2012 07:37 AM   
3 2725 By grasshopper
28 Mar 2012 06:04 AM   
Post How to report leaf cell area
started by tompy  on 19 Dec 2011 10:46 PM   
2 4194 By grasshopper
28 Mar 2012 06:02 AM   
Post Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor.
started by Thommandram  on 23 Mar 2012 02:04 PM   
0 2000 By Thommandram
23 Mar 2012 02:04 PM   
Post How to integrate a full-custom designed layout with a semi-custom designed microprocessor.
started by Thommandram  on 23 Mar 2012 12:46 PM   
0 1956 By Thommandram
23 Mar 2012 12:46 PM   
Post CCD check fails as Encounter cannot parse a design file which has a "generate" block in it
started by dp2402  on 14 Mar 2012 06:40 AM   
6 3341 By dp2402
15 Mar 2012 02:30 AM   
Post Cadence RTL Compiler: read_tcf vs read_vcd
started by mamsadegh  on 07 Mar 2012 10:01 AM   
1 2974 By grasshopper
07 Mar 2012 05:27 PM   
Post power estimation using rc
started by RCsyn  on 29 Feb 2012 12:41 PM   
0 2537 By RCsyn
29 Feb 2012 12:41 PM   
Post RC synthesis flows
started by sureshm  on 04 Feb 2012 10:09 AM   
4 4467 By sureshm
25 Feb 2012 08:26 PM   
Post RTL Synthesis
started by Orion007  on 23 Feb 2012 06:12 AM   
0 2613 By Orion007
23 Feb 2012 06:12 AM   
Post ask one question about the location of the reserve bit in register
started by redrabbit  on 09 Feb 2012 10:30 PM   
1 3006 By grasshopper
12 Feb 2012 04:57 PM   
Post TLU support for RC?
started by Alex Kli  on 08 Feb 2012 07:53 AM   
3 3418 By grasshopper
08 Feb 2012 08:43 AM   
Post unix shell command with slightly complicated commands
started by Rashed Islam  on 31 Jan 2012 11:19 AM   
7 4877 By grasshopper
01 Feb 2012 07:16 AM   
Post RTL Compiler: Remove Empty Modules
started by moogyd  on 31 Jan 2012 05:56 AM   
2 3403 By moogyd
31 Jan 2012 06:38 AM   
Post RC report gates
started by Stevan  on 13 Dec 2011 10:05 AM   
1 4203 By grasshopper
24 Jan 2012 12:27 PM   
Post RTL compiler - synthesis
started by Ivan13  on 15 Jan 2012 05:19 AM   
1 3424 By grasshopper
24 Jan 2012 12:13 PM   

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