Home > Community > Forums > Logic Design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Logic Design Forum

Page 9 of 28     First ... 5678910111213 ... Last
  Topics   Replies     Views     Last Post  
Post Best flow to map most key points before compare
started by AntonioL  on 28 Mar 2012 02:24 AM   
2 2861 By AntonioL
29 Mar 2012 11:50 PM   
Post RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement
started by mamsadegh  on 29 Mar 2012 02:37 AM   
0 2478 By mamsadegh
29 Mar 2012 02:37 AM   
Post RTL Compiler - "synthesize -to_generic" generated verilog netlist has delay!
started by mamsadegh  on 29 Mar 2012 02:27 AM   
0 2417 By mamsadegh
29 Mar 2012 02:27 AM   
Post RTL Compiler -- clock latency
started by amitram  on 17 Mar 2012 01:31 PM   
1 2446 By grasshopper
28 Mar 2012 06:10 AM   
Post I am using FreePDK45nm library. I couldn't synthesise a register file.
started by Thommandram  on 21 Mar 2012 10:01 AM   
1 2134 By grasshopper
28 Mar 2012 06:07 AM   
Post Procedure to define a new VHDL library in RTL compiler script
started by shustar  on 26 Mar 2012 07:37 AM   
3 2715 By grasshopper
28 Mar 2012 06:04 AM   
Post How to report leaf cell area
started by tompy  on 19 Dec 2011 10:46 PM   
2 4188 By grasshopper
28 Mar 2012 06:02 AM   
Post Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor.
started by Thommandram  on 23 Mar 2012 02:04 PM   
0 1993 By Thommandram
23 Mar 2012 02:04 PM   
Post How to integrate a full-custom designed layout with a semi-custom designed microprocessor.
started by Thommandram  on 23 Mar 2012 12:46 PM   
0 1950 By Thommandram
23 Mar 2012 12:46 PM   
Post CCD check fails as Encounter cannot parse a design file which has a "generate" block in it
started by dp2402  on 14 Mar 2012 06:40 AM   
6 3323 By dp2402
15 Mar 2012 02:30 AM   
Post Cadence RTL Compiler: read_tcf vs read_vcd
started by mamsadegh  on 07 Mar 2012 10:01 AM   
1 2962 By grasshopper
07 Mar 2012 05:27 PM   
Post power estimation using rc
started by RCsyn  on 29 Feb 2012 12:41 PM   
0 2532 By RCsyn
29 Feb 2012 12:41 PM   
Post RC synthesis flows
started by sureshm  on 04 Feb 2012 10:09 AM   
4 4450 By sureshm
25 Feb 2012 08:26 PM   
Post RTL Synthesis
started by Orion007  on 23 Feb 2012 06:12 AM   
0 2611 By Orion007
23 Feb 2012 06:12 AM   
Post ask one question about the location of the reserve bit in register
started by redrabbit  on 09 Feb 2012 10:30 PM   
1 3003 By grasshopper
12 Feb 2012 04:57 PM   
Post TLU support for RC?
started by Alex Kli  on 08 Feb 2012 07:53 AM   
3 3404 By grasshopper
08 Feb 2012 08:43 AM   
Post unix shell command with slightly complicated commands
started by Rashed Islam  on 31 Jan 2012 11:19 AM   
7 4857 By grasshopper
01 Feb 2012 07:16 AM   
Post RTL Compiler: Remove Empty Modules
started by moogyd  on 31 Jan 2012 05:56 AM   
2 3395 By moogyd
31 Jan 2012 06:38 AM   
Post RC report gates
started by Stevan  on 13 Dec 2011 10:05 AM   
1 4197 By grasshopper
24 Jan 2012 12:27 PM   
Post RTL compiler - synthesis
started by Ivan13  on 15 Jan 2012 05:19 AM   
1 3415 By grasshopper
24 Jan 2012 12:13 PM   

Page 9 of 28     First ... 5678910111213 ... Last

There are 2220 guest(s) and 2 member(s) online:
dschaefer, madhanmo

Most Active Users
1. dschaefer (50)   

Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.