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Logic Design Forum

Page 8 of 28     First ... 456789101112 ... Last
  Topics   Replies     Views     Last Post  
Post Standard Cell Library Design
started by pmuppala  on 15 Jul 2010 02:21 PM   
1 3046 By gentle
14 Jul 2012 08:38 AM   
Post dsn-files
started by wschira  on 14 Jul 2012 06:17 AM   
0 2204 By wschira
14 Jul 2012 06:17 AM   
Post .so cell import ?
started by DavidRo  on 13 Jul 2012 06:02 AM   
0 1847 By DavidRo
13 Jul 2012 06:02 AM   
Post RC-compiler Error create isolation rule and retention rule failed.....
started by yasir khan  on 06 Jul 2012 06:57 AM   
0 2156 By yasir khan
06 Jul 2012 06:57 AM   
Post CPF_Read Issue
started by affaqq  on 19 Jun 2012 09:37 AM   
2 2698 By tstark
19 Jun 2012 10:18 AM   
Post clock tree design
started by cupidsd  on 24 May 2012 09:38 AM   
0 3377 By cupidsd
24 May 2012 09:38 AM   
Post How to see power trace
started by ganeshK2012  on 21 May 2012 02:23 PM   
0 3448 By ganeshK2012
21 May 2012 02:23 PM   
Post VCD and irun
started by ganeshK2012  on 18 May 2012 06:37 AM   
1 4109 By Mickey
18 May 2012 09:19 AM   
Post Difference Between PLE, Spatial, Physical
started by sureshm  on 08 May 2012 10:33 PM   
1 3992 By grasshopper
16 May 2012 03:27 AM   
Post Any comments on the RC Physical Timing co-relation with EDI?
started by sureshm  on 08 May 2012 10:45 PM   
1 3835 By grasshopper
16 May 2012 03:13 AM   
Post Simulating verilog using cadence
started by MTP3  on 11 May 2012 11:53 AM   
1 3772 By MTP3
11 May 2012 08:10 PM   
Post Regarding retiming....which license is required
started by ChInNi miSSing  on 19 Mar 2011 02:00 AM   
1 4096 By mclarke
07 May 2012 12:01 PM   
Post Check out Conformal documentation via its web interface!
started by hummingbird  on 02 May 2012 12:27 PM   
1 3561 By tstark
03 May 2012 01:49 PM   
Post Why boundary_opto cause to LEC fail?
started by PengpengHao  on 18 Apr 2012 10:56 PM   
1 3925 By tstark
01 May 2012 05:59 PM   
Post Propagate a clock from .LIB of a block
started by randomax  on 30 Apr 2012 10:49 PM   
0 3359 By randomax
30 Apr 2012 10:49 PM   
Post How to synthesize without scan cell replacement
started by Maso  on 16 Apr 2012 06:15 PM   
7 5702 By Maso
19 Apr 2012 10:26 PM   
Post Checking equivalence of buffer trees
started by BufferTree  on 18 Apr 2012 01:12 PM   
1 3460 By tstark
19 Apr 2012 07:26 PM   
Post How to calculate speed for each path_group in RTL Compiler
started by Maso  on 11 Apr 2012 05:29 AM   
2 3198 By Maso
12 Apr 2012 07:12 PM   
Post How can I remove module before writing whole netlist out
started by Maso  on 02 Apr 2012 12:29 AM   
2 3324 By Maso
02 Apr 2012 06:22 PM   
Post Cadence encounter(9.x) crashes while doing "verify_geometries"
started by Akatyal22  on 02 Apr 2012 10:53 AM   
0 2856 By Akatyal22
02 Apr 2012 10:53 AM   

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