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Logic Design Forum

Page 7 of 28     First ... 34567891011 ... Last
  Topics   Replies     Views     Last Post  
Post How to add Synthesizable delay into the module
started by Maheshnb  on 11 Nov 2012 07:53 AM   
1 686 By grasshopper
11 Nov 2012 11:34 AM   
Post max_fanout constraint
started by tanyacool  on 06 Nov 2012 10:04 PM   
0 874 By tanyacool
06 Nov 2012 10:04 PM   
Post how to find out the FFs connected to the output of a selected FF
started by gops  on 06 Nov 2012 07:32 AM   
1 701 By bmiller
06 Nov 2012 08:30 AM   
Post what dose pulse width mean in timing report
started by small5  on 06 Nov 2012 12:45 AM   
0 844 By small5
06 Nov 2012 12:45 AM   
Post RTL Compiler synthesis commands for TDC design
started by Maheshnb  on 01 Nov 2012 09:06 AM   
0 931 By Maheshnb
01 Nov 2012 09:06 AM   
Post RC: to Remove PG pins from a Netlist..
started by Yemelya  on 22 Oct 2012 10:57 AM   
1 909 By bmiller
23 Oct 2012 07:39 AM   
Post Groups back annotaion (allegro to concept and back)
started by bdv005  on 22 Oct 2012 06:23 AM   
0 682 By bdv005
22 Oct 2012 06:23 AM   
Post Wanted to know the behaviour of RC on different SDC command
started by tanyacool  on 17 Oct 2012 02:04 AM   
2 1164 By tanyacool
18 Oct 2012 11:48 PM   
Post Outputting a synthesized file in reverse order
started by Ankur S  on 13 Oct 2012 12:44 PM   
0 711 By Ankur S
13 Oct 2012 12:44 PM   
Post LEC issue - "elaborate" vs. "synthesize -to_generic"
started by Yemelya  on 05 Oct 2012 07:47 AM   
1 1364 By bmiller
09 Oct 2012 09:35 AM   
Post -binding flag is ignored by ncelab
started by myonlyscreen  on 04 Oct 2012 08:41 AM   
3 2464 By TAM1
04 Oct 2012 03:54 PM   
Post area calculation by RC
started by tanyacool  on 04 Oct 2012 07:14 AM   
1 863 By bmiller
04 Oct 2012 08:10 AM   
Post Should I bother about the PLL delay?
started by gops  on 29 Jul 2012 08:21 AM   
2 2149 By grasshopper
05 Sep 2012 06:23 AM   
Post RTL Compiler tutorial
started by ubbala  on 01 Sep 2012 08:11 AM   
1 1763 By grasshopper
05 Sep 2012 06:10 AM   
Post How to Simulate 64-bit VHDL Code in Cadence?
started by shahein  on 04 Sep 2012 01:17 AM   
0 1072 By shahein
04 Sep 2012 01:17 AM   
Post LEC report additional FF
started by theodoredj  on 01 Mar 2012 07:33 PM   
7 4491 By affaqq
17 Aug 2012 02:43 PM   
Post LEC and Designware components
started by jlang  on 17 Aug 2012 12:21 PM   
1 1149 By affaqq
17 Aug 2012 12:22 PM   
Post how to map a particular library cell to a component
started by gops  on 29 Jul 2012 08:14 AM   
1 1754 By renobreint
14 Aug 2012 02:30 AM   
Post CDC Functional Checks taking too much time.
started by arunvaidya  on 19 Jun 2012 11:45 PM   
3 3090 By arunvaidya
23 Jul 2012 04:29 AM   
Post RTL Compiler: DFT Checks and non controllable/observable I/O
started by moogyd  on 31 Jan 2012 06:01 AM   
6 7205 By moogyd
19 Jul 2012 08:24 AM   

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