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Logic Design Forum

Page 6 of 28     First ... 2345678910 ... Last
  Topics   Replies     Views     Last Post  
Post Conformal-LP : Understanding liberty files.
started by nitint08  on 15 Jan 2013 02:04 AM   
6 2287 By NTlp
24 Jan 2013 11:22 PM   
Post RTL Complier flow with clock gating and scan insertion
started by Terry2000  on 17 Jan 2013 07:20 AM   
2 1182 By Terry2000
18 Jan 2013 09:23 AM   
Post Rtl Compiler behaviour on clock
started by tanyacool  on 16 Jan 2013 03:38 AM   
3 1028 By grasshopper
17 Jan 2013 06:34 AM   
Post no constraints on hierarchial boundaries
started by tanyacool  on 16 Jan 2013 11:08 PM   
1 661 By grasshopper
17 Jan 2013 06:30 AM   
Post How do we exclued delay cells in RC
started by tanyacool  on 16 Jan 2013 11:01 PM   
1 744 By grasshopper
17 Jan 2013 06:28 AM   
Post Conformal-LP : CPF_LIB1 not flagging.
started by nitint08  on 15 Jan 2013 10:36 PM   
1 679 By tstark
16 Jan 2013 06:22 PM   
Post Conformal LP : Merging CPF files.
started by nitint08  on 15 Jan 2013 02:03 AM   
1 742 By tstark
16 Jan 2013 06:15 PM   
Post difference between Random Resistance faults and deterministic faults?
started by vipul982  on 15 Jan 2013 04:15 AM   
1 1031 By bmiller
15 Jan 2013 06:57 AM   
Post How do I insert test point in the model?
started by vipul982  on 15 Jan 2013 01:26 AM   
0 817 By vipul982
15 Jan 2013 01:26 AM   
Post test procedure in Cadence encounter test tool?
started by vipul982  on 10 Jan 2013 05:19 AM   
4 1242 By vipul982
15 Jan 2013 01:21 AM   
Post Does test compaction reduces tester time or memory or both?
started by vipul982  on 02 Jan 2013 10:41 PM   
2 769 By vipul982
10 Jan 2013 05:20 AM   
Post how to connect multi clock domians to only one scan chain
started by MoKhairy  on 09 Jan 2013 03:38 AM   
1 895 By bmiller
09 Jan 2013 08:02 AM   
Post dft settings during DFT scan insertion
started by tanyacool  on 29 Oct 2012 05:40 AM   
4 1622 By nannasin28
07 Jan 2013 11:15 PM   
Post Reg .VCD file generation
started by Music  on 11 Nov 2009 09:14 AM   
8 6245 By nannasin28
07 Jan 2013 11:14 PM   
Post How to handle pre defined generated clocks in .libs.
started by sureshm  on 04 Jan 2013 08:28 AM   
0 803 By sureshm
04 Jan 2013 08:28 AM   
Post MBIST insertion using RC tool
started by Srikanth Y  on 19 Dec 2012 11:50 PM   
2 1167 By Srikanth Y
21 Dec 2012 02:09 AM   
Post Need help on forward body biasing and CSAFF&CHLFF circuit
started by ntus  on 11 Dec 2012 06:53 PM   
0 709 By ntus
11 Dec 2012 06:53 PM   
Post How to give a bit string as input in cadence virtuose spectre?
started by bsddsb  on 27 Nov 2012 03:34 AM   
0 931 By bsddsb
27 Nov 2012 03:34 AM   
Post Trouble with reading vcd file in RC 11.2
started by Chongxi  on 20 Nov 2012 01:58 PM   
1 766 By grasshopper
21 Nov 2012 03:13 AM   
Post RTL Compiler, Min Libraries and CPF
started by moogyd  on 19 Jul 2012 08:39 AM   
3 2604 By grasshopper
11 Nov 2012 11:44 AM   

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