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Logic Design Forum

Page 4 of 28     First 12345678 ... Last
  Topics   Replies     Views     Last Post  
Post RTL compiler command for retaining design hierarchy
started by dkhan  on 07 Jul 2013 02:39 PM   
2 6977 By dkhan
09 Jul 2013 08:43 AM   
Post how to compare designware like DW02_multp with LEC
started by codefire  on 27 Sep 2008 08:48 PM   
3 5833 By conformalfan
20 Jun 2013 10:27 AM   
Post Conformal LEC Dofile Arguments.
started by scrip  on 24 May 2013 11:20 AM   
3 3368 By tstark
20 Jun 2013 09:38 AM   
Post RTL compiler to minimize area
started by Hamzah  on 14 Jun 2013 04:04 PM   
4 1246 By Hamzah
19 Jun 2013 02:41 PM   
Post Creating a reset scan test using Encounter Test
started by glennramalho  on 19 Jun 2013 12:53 PM   
0 489 By glennramalho
19 Jun 2013 12:53 PM   
Post using ModelSim/QuestaSim VCD file in RTL compiler
started by dkhan  on 18 Jun 2013 12:53 AM   
3 1235 By bmiller
18 Jun 2013 11:50 AM   
Post set_false_path -through and set_load on the output ports
started by beginer  on 31 Mar 2013 05:53 PM   
1 1058 By grasshopper
18 Jun 2013 06:17 AM   
Post How do I delete clock groups (created via set_clock_groups)
started by moogydmaxim  on 03 May 2013 12:14 PM   
1 901 By grasshopper
18 Jun 2013 06:15 AM   
Post How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler
started by lvcargnini  on 14 May 2013 08:23 AM   
1 1158 By grasshopper
18 Jun 2013 06:08 AM   
Post cell_leakage_power
started by msanyal  on 17 May 2013 09:20 AM   
1 616 By bmiller
21 May 2013 12:19 PM   
Post Scan mode and scan chain control from internal registers
started by Sinjeetp  on 26 Apr 2013 06:25 PM   
4 1332 By Sinjeetp
15 May 2013 11:23 AM   
Post Exclude Paramter name/value during module generation in LEC
started by Rafeeq2129  on 10 May 2013 03:05 AM   
2 750 By Rafeeq2129
13 May 2013 02:51 AM   
Post Two warnings(external_delay and CSA rejected)
started by 20050710212  on 08 May 2013 05:47 AM   
1 625 By grasshopper
09 May 2013 06:04 AM   
Post module naming with hexadecimal values
started by Rafeeq2129  on 24 Apr 2013 12:19 AM   
2 942 By tstark
29 Apr 2013 10:51 AM   
Post Command to Store, Restore a RTL Compiler session
started by beginer  on 01 Mar 2013 08:48 PM   
3 1098 By grasshopper
29 Apr 2013 05:49 AM   
Post RTL Compiler: VCD Annotation and CPF
started by moogydmaxim  on 23 Apr 2013 01:20 AM   
4 1019 By moogydmaxim
26 Apr 2013 01:52 AM   
Post Verilog simulation using verilog XL
started by OLyonnais  on 09 Jun 2010 06:10 AM   
2 2406 By tstark
22 Apr 2013 09:59 AM   
Post Error with Vendor-contributed Models in Simulation
started by sns22  on 19 Apr 2013 08:40 AM   
1 742 By oldmouldy
22 Apr 2013 05:28 AM   
Post What does area reported by RTL compiler mean?
started by rexnyu  on 05 Apr 2013 09:29 AM   
2 1269 By rexnyu
14 Apr 2013 08:46 AM   
Post ELC - Generic PDK 45 version 3.5 - Redefinition error
started by kmmankad  on 03 Apr 2013 11:37 PM   
0 805 By kmmankad
03 Apr 2013 11:37 PM   

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