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Logic Design Forum

Page 3 of 28     First 1234567 ... Last
  Topics   Replies     Views     Last Post  
Post where can we get the RAK
started by tanyacool  on 10 Sep 2013 10:17 AM   
2 7993 By Azar990
10 Nov 2013 07:26 PM   
Post Asynchronous FIFO design
started by abhinavpr  on 18 Jun 2013 03:56 AM   
7 10003 By KennyWylies
27 Oct 2013 09:31 AM   
Post where can i get gate.lib
started by Anasios  on 15 Oct 2013 02:18 AM   
1 7970 By oldmouldy
15 Oct 2013 07:52 AM   
Post RC: set_min/max_delay breaks the constrained paths
started by Sporadic Crash  on 26 Mar 2013 05:06 AM   
3 8667 By sjoshi
12 Sep 2013 12:15 AM   
Post What does Constant hierarchical Pin(s) means in RTL compiler?
started by Bardia B  on 09 Sep 2013 11:47 AM   
1 7954 By bmiller
11 Sep 2013 10:48 AM   
Post *E,TRFILEIO: file I/O Error using textio.all library in Sigasi
started by melisanthi  on 09 Sep 2013 01:06 PM   
0 7807 By melisanthi
09 Sep 2013 01:06 PM   
Post unwanted "\" in netlist
started by tompy  on 03 Sep 2013 03:21 AM   
2 7867 By tompy
03 Sep 2013 07:14 PM   
Post The error of Synthesis
started by bravepanda  on 03 Sep 2013 01:53 PM   
0 7748 By bravepanda
03 Sep 2013 01:53 PM   
Post Question about the multiplier
started by bravepanda  on 02 Sep 2013 08:07 AM   
3 7884 By grasshopper
03 Sep 2013 10:47 AM   
Post Library requirements during elaboration stage
started by tanyacool  on 20 Aug 2013 02:52 AM   
2 4971 By tanyacool
20 Aug 2013 10:44 PM   
Post how to define scan chains in RC
started by tanyacool  on 20 Aug 2013 03:32 AM   
1 4897 By grasshopper
20 Aug 2013 07:39 AM   
Post Include a IP netlist during Synthesis of a complete design
started by Bapaiah  on 14 Aug 2013 02:41 AM   
2 3796 By Bapaiah
18 Aug 2013 09:53 PM   
Post RC - read_hdl
started by Yemelya  on 31 Jul 2013 07:52 AM   
2 3947 By Yemelya
31 Jul 2013 10:19 AM   
Post Does clock power included in Power Report ?
started by dkhan  on 27 Jul 2013 02:23 PM   
2 4016 By dkhan
29 Jul 2013 10:02 AM   
Post power differences after post-syn using VCD
started by leez2006  on 24 Jul 2013 04:24 AM   
2 3901 By leez2006
25 Jul 2013 06:18 PM   
Post how to add synthesizable delay in design
started by yasir khan  on 14 Aug 2012 03:19 PM   
1 4920 By Paul Bibin
20 Jul 2013 11:26 AM   
Post How to avoid unwanted removal of logic during synthesis
started by dkhan  on 07 Jul 2013 04:08 AM   
2 4112 By dkhan
09 Jul 2013 08:51 AM   
Post RTL compiler command for retaining design hierarchy
started by dkhan  on 07 Jul 2013 02:39 PM   
2 5169 By dkhan
09 Jul 2013 08:43 AM   
Post how to compare designware like DW02_multp with LEC
started by codefire  on 27 Sep 2008 08:48 PM   
3 5753 By conformalfan
20 Jun 2013 10:27 AM   
Post Conformal LEC Dofile Arguments.
started by scrip  on 24 May 2013 11:20 AM   
3 3223 By tstark
20 Jun 2013 09:38 AM   

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