Home > Community > Forums > Logic Design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Logic Design Forum

Page 20 of 27     First ... 161718192021222324 ... Last
  Topics   Replies     Views     Last Post  
Post Can we read extracted timing model in RC
started by archive  on 24 Mar 2008 06:35 AM   
1 1060 By archive
24 Mar 2008 06:35 AM   
Post Regarding sample dofile for in lec verify mode
started by archive  on 23 Mar 2008 08:20 AM   
4 2073 By archive
23 Mar 2008 08:20 AM   
Post Clock gating
started by archive  on 19 Mar 2008 06:11 PM   
1 1101 By archive
19 Mar 2008 06:11 PM   
Post How to trace flops with constant inputs in Conformal?
started by archive  on 19 Mar 2008 06:06 PM   
1 887 By archive
19 Mar 2008 06:06 PM   
Post Unmapped point (extra)
started by archive  on 17 Mar 2008 05:21 AM   
1 1255 By archive
17 Mar 2008 05:21 AM   
Post ncelab: *W,BIGWBS
started by archive  on 12 Mar 2008 04:47 PM   
4 1870 By archive
12 Mar 2008 04:47 PM   
Post inverted equivalent points
started by archive  on 11 Mar 2008 02:31 AM   
1 1629 By archive
11 Mar 2008 02:31 AM   
Post help needed
started by archive  on 10 Mar 2008 11:19 PM   
1 863 By archive
10 Mar 2008 11:19 PM   
Post Non-equivalences due to different device.
started by archive  on 10 Mar 2008 06:20 AM   
1 1143 By archive
10 Mar 2008 06:20 AM   
Post flattening synthetic operators
started by archive  on 08 Mar 2008 12:55 AM   
2 1249 By archive
08 Mar 2008 12:55 AM   
Post dont_use option in Buildgates
started by archive  on 07 Mar 2008 02:20 PM   
2 1105 By archive
07 Mar 2008 02:20 PM   
Post Using Ocean scripts to calculate simulation data.
started by archive  on 06 Mar 2008 02:18 PM   
3 1720 By archive
06 Mar 2008 02:18 PM   
Post verilog .v lib vs synopsis .lib
started by archive  on 29 Feb 2008 10:10 AM   
1 1626 By archive
29 Feb 2008 10:10 AM   
Post Unmapped point (not-mapped) issue
started by archive  on 12 Feb 2008 03:23 AM   
3 2714 By archive
12 Feb 2008 03:23 AM   
Post few ques ..
started by archive  on 06 Feb 2008 05:50 PM   
1 887 By archive
06 Feb 2008 05:50 PM   
Post How do you find the driving cell?
started by archive  on 04 Feb 2008 07:11 AM   
4 1344 By archive
04 Feb 2008 07:11 AM   
Post Conformal struggles to resolve abort points (due to complex logic)
started by archive  on 31 Jan 2008 07:58 AM   
3 3484 By archive
31 Jan 2008 07:58 AM   
Post report on FFs, Latchs
started by archive  on 25 Jan 2008 02:59 PM   
1 958 By archive
25 Jan 2008 02:59 PM   
Post flat netlist
started by archive  on 17 Jan 2008 09:27 AM   
4 2313 By archive
17 Jan 2008 09:27 AM   
Post RTL vs. gate netlist verification mapping problem
started by archive  on 16 Jan 2008 08:21 AM   
1 1098 By archive
16 Jan 2008 08:21 AM   

Page 20 of 27     First ... 161718192021222324 ... Last

There are 1001 guest(s) and 1 member(s) online:
kingscuprulse

Most Active Users


Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.