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Logic Design Forum

Page 2 of 28     First 123456 ... Last
  Topics   Replies     Views     Last Post  
Post Help on LEC failure between compile netlist vs. compile_incr netlist from DC
started by r u verified  on 05 Mar 2014 05:29 PM   
0 2285 By r u verified
05 Mar 2014 05:29 PM   
Post CIS DB source
started by dpiccardi  on 04 Mar 2014 06:22 AM   
0 740 By dpiccardi
04 Mar 2014 06:22 AM   
Post preserving a subdesign from optimization
started by P V S Shastry  on 30 Dec 2013 05:09 AM   
2 4850 By grasshopper
27 Feb 2014 12:25 PM   
Post how to identify unique nets connected to preset/clear pins of all FFs in a scope
started by Sporadic Crash  on 07 Jan 2014 12:07 PM   
1 4931 By grasshopper
27 Feb 2014 11:01 AM   
Post delay between 2 signals
started by vvgulyaev  on 25 Feb 2014 02:05 AM   
1 1748 By grasshopper
27 Feb 2014 10:37 AM   
Post conformal
started by Indira S  on 11 Feb 2014 01:27 AM   
0 1877 By Indira S
11 Feb 2014 01:27 AM   
Post conformal lec
started by Indira S  on 10 Feb 2014 02:30 AM   
0 1944 By Indira S
10 Feb 2014 02:30 AM   
Post Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist
started by Rafeeq2129  on 06 Mar 2013 03:03 AM   
12 5930 By tstark
05 Feb 2014 06:37 PM   
Post conformal_lec 12.0
started by Indira S  on 29 Jan 2014 02:33 AM   
1 3198 By tstark
05 Feb 2014 06:25 PM   
Post Design Entry HDL - Disabling Constraint Manager
started by Crispy  on 05 Feb 2014 09:00 AM   
0 2388 By Crispy
05 Feb 2014 09:00 AM   
Post conformal
started by Indira S  on 30 Jan 2014 02:20 AM   
0 3018 By Indira S
30 Jan 2014 02:20 AM   
Post conformal -Lec
started by Indira S  on 28 Jan 2014 02:20 AM   
1 3412 By tstark
28 Jan 2014 03:22 PM   
Post Conformal- LEC
started by Indira S  on 16 Jan 2014 08:35 PM   
1 3961 By tstark
17 Jan 2014 11:04 AM   
Post Algorithm used for implementation of Division
started by S0MA  on 02 Jan 2014 11:00 PM   
2 4735 By S0MA
09 Jan 2014 10:19 PM   
Post Instance name mismatch between .v and .sdf writen from RTL compiler
started by zczc999  on 23 Dec 2013 07:32 AM   
0 4853 By zczc999
23 Dec 2013 07:32 AM   
Post Preserving structure in RTL Compiler
started by Aram Shahinyan  on 17 Dec 2013 06:46 AM   
7 5264 By grasshopper
23 Dec 2013 06:02 AM   
Post CIS Schematic Page numbering
started by budnoel  on 20 Dec 2013 11:31 AM   
0 4841 By budnoel
20 Dec 2013 11:31 AM   
Post How to set_current_module in RTL Compiler??
started by archive  on 07 Jul 2007 01:00 PM   
10 7500 By jojo57006
16 Dec 2013 11:39 PM   
Post re-target technology node
started by DDEOTA  on 03 Dec 2013 06:55 PM   
0 4945 By DDEOTA
03 Dec 2013 06:55 PM   
Post Force RTL compiler not to optimize certain part of the design
started by rexnyu  on 20 Nov 2013 01:55 PM   
1 5670 By grasshopper
20 Nov 2013 03:03 PM   

Page 2 of 28     First 123456 ... Last

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