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Logic Design Forum

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Sticky Logic Design Forum Posting Guidelines
started by tstark  on 06 Feb 2014 11:02 AM   
0 2458 By tstark
06 Feb 2014 11:02 AM   
Post Avoid race condition at SPI_slave synthesis
started by alphus  on 21 Apr 2014 03:03 AM   
0 14 By alphus
21 Apr 2014 03:03 AM   
Post Unsupported SDC Commands(remove_attribute) in RC
started by doydodo  on 21 Apr 2014 12:37 AM   
0 26 By doydodo
21 Apr 2014 12:37 AM   
Post how to synthesize delay elements in RTL complier
started by micro469  on 17 Apr 2014 11:25 AM   
2 36 By micro469
17 Apr 2014 11:05 PM   
Post How to simulate after synthesis in NC launch or NC sim
started by micro469  on 17 Apr 2014 11:37 AM   
1 36 By grasshopper
17 Apr 2014 08:24 PM   
Post conformal LEC
started by Indira S  on 13 Apr 2014 11:28 PM   
0 32 By Indira S
13 Apr 2014 11:28 PM   
Post clock gating in RC
started by doydodo  on 09 Apr 2014 11:33 PM   
1 38 By bmiller
10 Apr 2014 08:37 AM   
Post Conformal ECO - Equivalanece check
started by Prashant M  on 09 Apr 2014 04:52 AM   
0 128 By Prashant M
09 Apr 2014 04:52 AM   
Post How to set ignore for some of blackbox pins in LEC?
started by lc337199  on 01 Apr 2014 04:40 PM   
1 185 By lc337199
04 Apr 2014 03:31 PM   
Post LEC - Conformal RTL to netlist mismatch
started by hnfq  on 11 Jul 2012 12:21 PM   
8 4278 By Manoj Kumar S
03 Apr 2014 12:14 AM   
Post external delay
started by IBKRAJU  on 03 Mar 2014 08:54 AM   
1 794 By grasshopper
28 Mar 2014 06:18 AM   
Post Blackboxing in Conformal LEC.
started by Bhawan  on 28 Mar 2014 03:07 AM   
0 604 By Bhawan
28 Mar 2014 03:07 AM   
Post Reading HDL files in RC
started by archive  on 03 Jan 2007 12:44 AM   
4 1304 By nagarjunsingir
20 Mar 2014 05:39 AM   
Post how to find power of a design based on inputs given to the design using cadence
started by samhitha nr  on 18 Mar 2014 09:19 AM   
1 390 By grasshopper
20 Mar 2014 03:13 AM   
Post Help on LEC failure between compile netlist vs. compile_incr netlist from DC
started by r u verified  on 05 Mar 2014 05:29 PM   
0 584 By r u verified
05 Mar 2014 05:29 PM   
Post CIS DB source
started by dpiccardi  on 04 Mar 2014 06:22 AM   
0 602 By dpiccardi
04 Mar 2014 06:22 AM   
Post preserving a subdesign from optimization
started by P V S Shastry  on 30 Dec 2013 05:09 AM   
2 4767 By grasshopper
27 Feb 2014 12:25 PM   
Post how to identify unique nets connected to preset/clear pins of all FFs in a scope
started by Sporadic Crash  on 07 Jan 2014 12:07 PM   
1 4742 By grasshopper
27 Feb 2014 11:01 AM   
Post delay between 2 signals
started by vvgulyaev  on 25 Feb 2014 02:05 AM   
1 1700 By grasshopper
27 Feb 2014 10:37 AM   
Post conformal
started by Indira S  on 11 Feb 2014 01:27 AM   
0 1829 By Indira S
11 Feb 2014 01:27 AM   

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