Home > Community > Forums > Logic Design
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
 

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Logic Design Forum

Page 1 of 25     12345 ... Last
  Topics   Replies     Views     Last Post  
Post cell_leakage_power
started by msanyal  on Yesterday at 09:20 AM    		0 21 By msanyal
Yesterday at 09:20 AM   
Post Scan mode and scan chain control from internal registers
started by Sinjeetp  on 26 Apr 2013 06:25 PM    		4 160 By Sinjeetp
15 May 2013 11:23 AM   
Post How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler
started by lvcargnini  on 14 May 2013 08:23 AM    		0 41 By lvcargnini
14 May 2013 08:23 AM   
Post Exclude Paramter name/value during module generation in LEC
started by Rafeeq2129  on 10 May 2013 03:05 AM    		2 73 By Rafeeq2129
13 May 2013 02:51 AM   
Post Two warnings(external_delay and CSA rejected)
started by 20050710212  on 08 May 2013 05:47 AM    		1 75 By grasshopper
09 May 2013 06:04 AM   
Post How do I delete clock groups (created via set_clock_groups)
started by moogydmaxim  on 03 May 2013 12:14 PM    		0 96 By moogydmaxim
03 May 2013 12:14 PM   
Post module naming with hexadecimal values
started by Rafeeq2129  on 24 Apr 2013 12:19 AM    		2 172 By tstark
29 Apr 2013 10:51 AM   
Post Command to Store, Restore a RTL Compiler session
started by beginer  on 01 Mar 2013 08:48 PM    		3 357 By grasshopper
29 Apr 2013 05:49 AM   
Post RTL Compiler: VCD Annotation and CPF
started by moogydmaxim  on 23 Apr 2013 01:20 AM    		4 170 By moogydmaxim
26 Apr 2013 01:52 AM   
Post Verilog simulation using verilog XL
started by OLyonnais  on 09 Jun 2010 06:10 AM    		2 1605 By tstark
22 Apr 2013 09:59 AM   
Post Error with Vendor-contributed Models in Simulation
started by sns22  on 19 Apr 2013 08:40 AM    		1 138 By oldmouldy
22 Apr 2013 05:28 AM   
Post Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist
started by Rafeeq2129  on 06 Mar 2013 03:03 AM    		9 651 By tstark
18 Apr 2013 05:00 PM   
Post What does area reported by RTL compiler mean?
started by rexnyu  on 05 Apr 2013 09:29 AM    		2 254 By rexnyu
14 Apr 2013 08:46 AM   
Post ELC - Generic PDK 45 version 3.5 - Redefinition error
started by kmmankad  on 03 Apr 2013 11:37 PM    		0 207 By kmmankad
03 Apr 2013 11:37 PM   
Post Power Difference between Analog Simulation and RTL complier estimation
started by GreenGraphene  on 25 Mar 2013 05:48 AM    		1 300 By Fotios Nt
02 Apr 2013 09:31 AM   
Post set_false_path -through and set_load on the output ports
started by beginer  on 31 Mar 2013 05:53 PM    		0 230 By beginer
31 Mar 2013 05:53 PM   
Post Problem occurs when reading vcd in RTL Compiler
started by rexnyu  on 26 Mar 2013 01:12 PM    		5 385 By rexnyu
28 Mar 2013 03:04 PM   
Post Where is 7400.olb ?
started by ArealPerson  on 27 Mar 2013 02:00 PM    		1 188 By oldmouldy
27 Mar 2013 02:43 PM   
Post Error : Verilog-2001 feature.
started by rexnyu  on 26 Mar 2013 09:23 AM    		1 202 By rexnyu
26 Mar 2013 10:24 AM   
Post RC: set_min/max_delay breaks the constrained paths
started by Sporadic Crash  on 26 Mar 2013 05:06 AM    		2 242 By Sporadic Crash
26 Mar 2013 07:22 AM   

Page 1 of 25     12345 ... Last

There are 15 guest(s) and 0 member(s) online:


Most Active Users


Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.