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Logic Design Forum

Page 1 of 21     12345 ... Last
  Topics   Replies     Views     Last Post  
Post clock tree design
started by cupidsd  on Yesterday at 09:38 AM    		0 43 By cupidsd
Yesterday at 09:38 AM   
Post How to see power trace
started by ganeshK2012  on 21 May 2012 02:23 PM    		0 153 By ganeshK2012
21 May 2012 02:23 PM   
Post VCD and irun
started by ganeshK2012  on 18 May 2012 06:37 AM    		1 243 By Mickey
18 May 2012 09:19 AM   
Post Difference Between PLE, Spatial, Physical
started by sureshm  on 08 May 2012 10:33 PM    		1 363 By grasshopper
16 May 2012 03:27 AM   
Post Any comments on the RC Physical Timing co-relation with EDI?
started by sureshm  on 08 May 2012 10:45 PM    		1 366 By grasshopper
16 May 2012 03:13 AM   
Post Simulating verilog using cadence
started by MTP3  on 11 May 2012 11:53 AM    		1 336 By MTP3
11 May 2012 08:10 PM   
Post Regarding retiming....which license is required
started by ChInNi miSSing  on 19 Mar 2011 02:00 AM    		1 697 By mclarke
07 May 2012 12:01 PM   
Post Check out Conformal documentation via its web interface!
started by hummingbird  on 02 May 2012 12:27 PM    		1 358 By tstark
03 May 2012 01:49 PM   
Post Why boundary_opto cause to LEC fail?
started by PengpengHao  on 18 Apr 2012 10:56 PM    		1 573 By tstark
01 May 2012 05:59 PM   
Post Propagate a clock from .LIB of a block
started by randomax  on 30 Apr 2012 10:49 PM    		0 363 By randomax
30 Apr 2012 10:49 PM   
Post How to synthesize without scan cell replacement
started by Maso  on 16 Apr 2012 06:15 PM    		7 663 By Maso
19 Apr 2012 10:26 PM   
Post Checking equivalence of buffer trees
started by BufferTree  on 18 Apr 2012 01:12 PM    		1 475 By tstark
19 Apr 2012 07:26 PM   
Post How to calculate speed for each path_group in RTL Compiler
started by Maso  on 11 Apr 2012 05:29 AM    		2 708 By Maso
12 Apr 2012 07:12 PM   
Post How can I remove module before writing whole netlist out
started by Maso  on 02 Apr 2012 12:29 AM    		2 911 By Maso
02 Apr 2012 06:22 PM   
Post Cadence encounter(9.x) crashes while doing "verify_geometries"
started by Akatyal22  on 02 Apr 2012 10:53 AM    		0 829 By Akatyal22
02 Apr 2012 10:53 AM   
Post Do you have issues using multibit flops
started by AntonioL  on 28 Mar 2012 02:29 AM    		1 1058 By tstark
02 Apr 2012 09:32 AM   
Post Hello. How to add a custom cell to the freePDK45nm standard cell library.
started by Thommandram  on 01 Apr 2012 09:49 AM    		1 854 By mcaruso
02 Apr 2012 06:41 AM   
Post Conformal ECO Flow Basic Question
started by moogyd  on 30 Mar 2012 09:19 AM    		1 1081 By hummingbird
30 Mar 2012 12:37 PM   
Post Best flow to map most key points before compare
started by AntonioL  on 28 Mar 2012 02:24 AM    		2 1100 By AntonioL
29 Mar 2012 11:50 PM   
Post RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement
started by mamsadegh  on 29 Mar 2012 02:37 AM    		0 1055 By mamsadegh
29 Mar 2012 02:37 AM   

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