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Functional Verification Forum

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Post problem about set profile
started by redrabbit  on 23 Feb 2012 11:23 PM    		1 2257 By StephenH
24 Feb 2012 12:19 AM   
Post one question about e hal --ignore or delete the post plz
started by redrabbit  on 22 Feb 2012 06:45 PM    		3 2542 By redrabbit
23 Feb 2012 11:08 PM   
Post NC VHDL "simulation error"
started by kovibb  on 23 Feb 2012 12:48 AM    		2 2586 By kovibb
23 Feb 2012 06:46 AM   
Post NC-verilog logical bug
started by Aiya  on 22 Feb 2012 11:10 PM    		5 2052 By StephenH
23 Feb 2012 02:24 AM   
Post Cadence OCP Master BFM Oveflow error
started by Joe12  on 20 Feb 2012 05:20 AM    		1 1444 By StephenH
20 Feb 2012 05:43 AM   
Post Non HTML coverage report generation using E-manager
started by bharathwajan  on 19 Feb 2012 06:09 PM    		2 2215 By bharathwajan
20 Feb 2012 03:35 AM   
Post wreal to logic connect module
started by diablo  on 13 Feb 2012 11:56 AM    		0 1877 By diablo
13 Feb 2012 11:56 AM   
Post syntax of the expand.cfg file created by Hierarchy-Editor
started by LeO99  on 09 Feb 2012 11:02 PM    		2 1965 By LeO99
13 Feb 2012 12:52 AM   
Post one question about vplan
started by redrabbit  on 07 Feb 2012 05:10 PM    		2 1841 By redrabbit
12 Feb 2012 06:15 PM   
Post the wave display...
started by sunjianty  on 05 Feb 2012 06:00 AM    		2 1908 By sunjianty
06 Feb 2012 12:34 AM   
Post how to merge the coverage report using IMC?
started by guest4cadence  on 12 Sep 2011 05:44 PM    		3 5935 By tpylant
03 Feb 2012 12:05 PM   
Post "No connection module found" Error
started by medeepak  on 02 Feb 2012 11:24 PM    		0 2151 By medeepak
02 Feb 2012 11:24 PM   
Post ask one question about one kind of error
started by redrabbit  on 31 Jan 2012 06:37 PM    		2 2185 By redrabbit
01 Feb 2012 11:54 PM   
Post play free slots
started by omar20  on 25 Jan 2012 09:58 AM    		0 1921 By omar20
25 Jan 2012 09:58 AM   
Post Training
started by techbee  on 24 Jan 2012 10:29 PM    		0 1932 By techbee
24 Jan 2012 10:29 PM   
Post compilation error in ncsc_run
started by ravi999  on 18 Jan 2012 10:52 PM    		0 1629 By ravi999
18 Jan 2012 10:52 PM   
Post how to optimize my code
started by redrabbit  on 13 Jan 2012 06:39 PM    		0 2160 By redrabbit
13 Jan 2012 06:39 PM   
Post reg : vhdl design with systemverilog testbench
started by Srikanth Madam  on 12 Jan 2012 01:38 AM    		0 2038 By Srikanth Madam
12 Jan 2012 01:38 AM   
Post ask one question about item range in e coverage
started by redrabbit  on 11 Jan 2012 12:19 AM    		0 1612 By redrabbit
11 Jan 2012 12:19 AM   
Post Enabling System Verilog Assertions with irun
started by samk  on 27 Sep 2011 07:21 PM    		1 3414 By tmackett
09 Jan 2012 04:37 PM   

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