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Digital Implementation Forum

Page 72 of 86     First ... 686970717273747576 ... Last
  Topics   Replies     Views     Last Post  
Post Number of Non Equivalence Points after comparison in LEC Conformal
started by Azhar  on 18 Aug 2008 12:17 AM   
1 2824 By Azhar
18 Aug 2008 12:20 AM   
Post Encounter/Nanoroute - fixing DRC violations while keeping critical pre-routes untouched
started by ccabal  on 15 Aug 2008 08:50 AM   
4 6742 By ccabal
15 Aug 2008 01:42 PM   
Post Disable clock gating check for a module.
started by Tongju  on 09 Aug 2008 01:23 PM   
0 3024 By Tongju
09 Aug 2008 01:23 PM   
Post How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"
started by naderi  on 06 Aug 2008 12:50 PM   
3 5852 By BobD
08 Aug 2008 12:01 PM   
Post Power estimation after synthesis and Place-&-route
started by naderi  on 01 Aug 2008 05:26 PM   
0 2378 By naderi
01 Aug 2008 05:26 PM   
Post about dbgGPSAutoCellFunction
started by archive  on 20 Jun 2008 05:53 PM   
5 3563 By tarekray
28 Jul 2008 11:31 PM   
Post Encounter doesn't find pgpin in the power pad
started by archive  on 04 Jul 2008 05:16 PM   
1 2762 By admin
25 Jul 2008 03:07 PM   
Post db command to return cell PG pin layer shape
started by archive  on 04 Jul 2008 04:38 AM   
0 2082 By archive
04 Jul 2008 04:38 AM   
Post power planning for AMS design
started by archive  on 01 Jul 2008 05:24 AM   
0 1994 By archive
01 Jul 2008 05:24 AM   
Post Clock Tree Latency Calculation Difference between reportClockTree & report_timing
started by archive  on 20 Jun 2008 03:35 AM   
4 4135 By archive
01 Jul 2008 02:18 AM   
Post encounter and conformal
started by archive  on 27 Jun 2008 01:47 AM   
0 1951 By archive
27 Jun 2008 01:47 AM   
Post About GCELLGRID and TRACK Statement in DEF
started by archive  on 26 Jun 2008 09:00 PM   
5 3405 By archive
26 Jun 2008 09:00 PM   
Post Is there any approach to add global power net despite DesignImport pwoer tab?
started by archive  on 24 Jun 2008 07:03 AM   
0 1920 By archive
24 Jun 2008 07:03 AM   
Post NanoRoute CRASH, need help.....VERSION SOC-E 52 Update 5
started by archive  on 24 Jun 2008 06:03 AM   
1 2087 By archive
24 Jun 2008 06:03 AM   
Post Is it a MUST to use capTable to do .13um design?
started by archive  on 23 Jun 2008 02:03 AM   
5 3120 By archive
23 Jun 2008 02:03 AM   
Post A warning when doing timing-driven NanoRoute, Urgent!
started by archive  on 20 Jun 2008 10:05 AM   
4 2738 By archive
20 Jun 2008 10:05 AM   
Post No matching .SUBCKT statement error in LVS check
started by archive  on 19 Jun 2008 08:12 AM   
8 6222 By archive
19 Jun 2008 08:12 AM   
Post Ideal nets in ETS
started by archive  on 17 Jun 2008 01:43 PM   
0 1728 By archive
17 Jun 2008 01:43 PM   
Post LVS after place&route may fail due to clock tree buffers
started by archive  on 16 Jun 2008 05:36 PM   
4 2557 By archive
16 Jun 2008 05:36 PM   
Post how to the error "Size of cell PADI45(80000,141660) is not an integer multiple of its site IOSite(20,400000)"
started by archive  on 13 Jun 2008 11:29 PM   
1 1802 By archive
13 Jun 2008 11:29 PM   

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