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Digital Implementation Forum

Page 4 of 85     First 12345678 ... Last
  Topics   Replies     Views     Last Post  
Post Dynamic Power Analysis
started by Meghz  on 31 Mar 2014 03:47 AM   
0 647 By Meghz
31 Mar 2014 03:47 AM   
Post Using RTL compiler PLE with DEF flow
started by tompy  on 27 Mar 2014 07:17 PM   
2 755 By grasshopper
28 Mar 2014 06:13 AM   
Post Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from
started by Haoxiang  on 06 Mar 2014 01:06 PM   
7 1719 By ajay01
20 Mar 2014 10:51 PM   
Post Regarding Domain crossing Net optmisation
started by victory2vicky  on 20 Mar 2014 12:22 AM   
0 196 By victory2vicky
20 Mar 2014 12:22 AM   
Post ostrich comparision issue
started by saikrishna  on 19 Mar 2014 02:03 AM   
1 315 By MJ Cad
19 Mar 2014 02:16 AM   
Post Tool is hanging while capacitance extraction in QRC 13.10.302 version
started by Sanath Yadav  on 13 Mar 2014 05:39 AM   
0 617 By Sanath Yadav
13 Mar 2014 05:39 AM   
Post how to add a global net
started by anil chatrathi  on 05 Jul 2012 07:40 AM   
4 2284 By wally1
10 Mar 2014 07:13 AM   
Post [Q] Edit Rules for SoC Encounter Stream-out Layer Map
started by M Refaat  on 07 Mar 2014 04:54 PM   
0 868 By M Refaat
07 Mar 2014 04:54 PM   
Post Via array is missing when importing DEF into Virtuoso
started by Ted345  on 07 Mar 2014 01:31 PM   
0 892 By Ted345
07 Mar 2014 01:31 PM   
Post postRoute in EDI13.2
started by BackerShu  on 01 Mar 2014 11:21 AM   
12 1480 By ajay01
05 Mar 2014 09:59 PM   
Post why my ELC internal power result so large???
started by Willvlsi  on 05 Mar 2014 04:14 PM   
0 613 By Willvlsi
05 Mar 2014 04:14 PM   
Post WARNING(SPMHNI-184): Device library warning detected.
started by maberu  on 03 Mar 2014 10:06 PM   
1 1305 By oldmouldy
05 Mar 2014 01:59 PM   
Post [Help] Warnings about metal layers in .map file
started by BackerShu  on 01 Mar 2014 02:07 PM   
3 1143 By Kari
04 Mar 2014 07:18 AM   
Post SOC Encounter producing functionality error
started by fieldy  on 28 Feb 2014 12:46 PM   
0 1172 By fieldy
28 Feb 2014 12:46 PM   
Post Timing constraine problem in synthesis
started by KUMARJAYA  on 27 Feb 2014 05:56 AM   
1 809 By grasshopper
27 Feb 2014 07:12 AM   
Post Spacing several instances of one standard cell using implant spacing rule
started by Guit56  on 27 Feb 2014 04:52 AM   
0 834 By Guit56
27 Feb 2014 04:52 AM   
Post TSMC 65nm GDS Import Problem
started by M Refaat  on 24 Feb 2014 02:04 PM   
3 1360 By Kari
26 Feb 2014 12:08 PM   
Post Gate array
started by jjgs  on 26 Feb 2014 09:48 AM   
0 934 By jjgs
26 Feb 2014 09:48 AM   
Post Missing VDD and VSS Connections in SoC Encounter Layout
started by PrasannaPC  on 26 Feb 2014 04:21 AM   
0 894 By PrasannaPC
26 Feb 2014 04:21 AM   
Post Mulitple AutoCTSRootPin - how CTS engine works
started by Chin Cypress  on 23 Feb 2014 02:05 AM   
0 1524 By Chin Cypress
23 Feb 2014 02:05 AM   

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