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Digital Implementation Forum

Page 1 of 86     12345 ... Last
  Topics   Replies     Views     Last Post  
Post relxpert vth degradation
started by Shiny  on 29 Aug 2014 12:13 PM   
0 151 By Shiny
29 Aug 2014 12:13 PM   
Post hold fixing in scan chains
started by chris06  on 28 Aug 2014 09:05 AM   
0 176 By chris06
28 Aug 2014 09:05 AM   
Post EDI Placement Density Screens Honored after Optimization?
started by Aram Shahinyan  on 01 Jul 2014 12:33 AM   
2 879 By Aram Shahinyan
20 Aug 2014 03:18 AM   
Post Power Analysis EPS vs. EDI
started by marten  on 18 Aug 2014 05:42 AM   
0 358 By marten
18 Aug 2014 05:42 AM   
Post Cannot find output terms for clock synthesis
started by FMRLI  on 31 Jul 2014 06:18 AM   
3 636 By wally1
08 Aug 2014 09:16 AM   
Post Pads on 3D IC
started by Costero  on 31 Jul 2014 02:50 AM   
0 560 By Costero
31 Jul 2014 02:50 AM   
Post Parasitic Extraction including floating stripes on top metal layer
started by salmancmosis  on 30 Jul 2014 12:53 AM   
0 549 By salmancmosis
30 Jul 2014 12:53 AM   
Post Litho physical analyser is used to reduce variations in 90 nm and below. What exactly is a hotspot in the context of LPA ?
started by GayathriJ  on 29 Jul 2014 10:24 PM   
0 553 By GayathriJ
29 Jul 2014 10:24 PM   
Post ELC not using spectre
started by Khenglish  on 23 Jul 2014 02:23 PM   
4 556 By Khenglish
25 Jul 2014 10:59 AM   
Post ELC cannot run db_spice
started by great ljx  on 23 Jul 2014 08:35 PM   
1 533 By Khenglish
24 Jul 2014 09:57 AM   
Post ELC (Simulation failed with the status 25600)
started by maple  on 24 Jul 2014 02:03 AM   
0 523 By maple
24 Jul 2014 02:03 AM   
Post Cadence ELC not recognising SPECTRE format
started by eklikeroomys  on 16 May 2011 03:08 AM   
4 3502 By maple
24 Jul 2014 01:43 AM   
Post script to run IRUN
started by tonio  on 23 Jul 2014 11:52 AM   
0 508 By tonio
23 Jul 2014 11:52 AM   
Post Import Synthesized Verilog Netlist to Virtuoso
started by gnaw  on 23 Jul 2014 07:40 AM   
0 522 By gnaw
23 Jul 2014 07:40 AM   
Post IC5141 CDL in skipping passive devices
started by lcaley  on 20 May 2013 01:19 PM   
2 1431 By csst
23 Jul 2014 02:56 AM   
Post Help with designing of NEMS switch in pspice
started by rajrevanth61  on 22 Jul 2014 09:38 AM   
0 499 By rajrevanth61
22 Jul 2014 09:38 AM   
Post Design partition in soc encounter 10.1
started by FMRLI  on 21 Jul 2014 10:56 AM   
0 503 By FMRLI
21 Jul 2014 10:56 AM   
Post Minarea violation in SOC encounter
started by Zahra  on 19 Jul 2014 03:20 AM   
0 509 By Zahra
19 Jul 2014 03:20 AM   
Post ncvhdl compilation error
started by livid  on 18 Jul 2014 04:47 AM   
0 470 By livid
18 Jul 2014 04:47 AM   
Post How to Characterize the timing information for level shifter with two supplys?
started by phoenixson  on 16 Jul 2014 07:04 PM   
0 488 By phoenixson
16 Jul 2014 07:04 PM   

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