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Digital Implementation Forum

Page 1 of 85     12345 ... Last
  Topics   Replies     Views     Last Post  
Post Design partition in soc encounter 10.1
started by FMRLI  on Yesterday at 10:56 AM   
0 7 By FMRLI
Yesterday at 10:56 AM   
Post Minarea violation in SOC encounter
started by Zahra  on 19 Jul 2014 03:20 AM   
0 25 By Zahra
19 Jul 2014 03:20 AM   
Post ncvhdl compilation error
started by livid  on 18 Jul 2014 04:47 AM   
0 8 By livid
18 Jul 2014 04:47 AM   
Post How to Characterize the timing information for level shifter with two supplys?
started by phoenixson  on 16 Jul 2014 07:04 PM   
0 24 By phoenixson
16 Jul 2014 07:04 PM   
Post Short violation
started by skow  on 14 Jul 2014 06:01 PM   
7 65 By skow
16 Jul 2014 10:24 AM   
Post EPS TMPDIR environment variable
started by jackIT  on 01 Jul 2014 10:02 AM   
2 394 By jackIT
15 Jul 2014 08:01 AM   
Post A problem in ELC (Encounter Library Characterizer)
started by Hyunny  on 23 Feb 2011 07:51 AM   
4 1684 By great ljx
12 Jul 2014 07:58 PM   
Post Parameters not being compiled in cell characterization
started by leonardoneves  on 13 Jun 2014 08:02 AM   
1 1061 By great ljx
10 Jul 2014 11:13 PM   
Post encounter library character cannot run db_spice
started by great ljx  on 10 Jul 2014 08:00 PM   
0 165 By great ljx
10 Jul 2014 08:00 PM   
Post Encounter library charaterizer could not read the hspice IBM model file
started by Satendra  on 16 Jun 2010 05:15 PM   
3 2390 By great ljx
10 Jul 2014 07:56 PM   
Post Special routes with opens
started by Stewan  on 09 Jul 2014 07:10 AM   
1 210 By wally1
09 Jul 2014 08:07 AM   
Post IR drop issue
started by Rajan Aggarwal  on 08 Jul 2014 10:47 AM   
0 238 By Rajan Aggarwal
08 Jul 2014 10:47 AM   
Post Implement TSGEN in IBM 9HP process
started by Khenglish  on 08 Jul 2014 09:32 AM   
0 238 By Khenglish
08 Jul 2014 09:32 AM   
Post sub threshold leakage power analysis and optimization
started by amuidhay  on 07 Jul 2014 09:54 PM   
0 221 By amuidhay
07 Jul 2014 09:54 PM   
Post Clock Tree Synthesis of a delay chain (tapped delay line)
started by randomax  on 06 Jul 2014 07:47 PM   
0 252 By randomax
06 Jul 2014 07:47 PM   
Post Nets Extraction
started by Anjali12  on 02 Jul 2014 07:36 AM   
0 350 By Anjali12
02 Jul 2014 07:36 AM   
Post Adding Routing blockage around boundary of block
started by NaikGangadhar  on 01 Jul 2014 11:54 PM   
0 363 By NaikGangadhar
01 Jul 2014 11:54 PM   
Post EDI Placement Density Screens Honored after Optimization?
started by Aram Shahinyan  on 01 Jul 2014 12:33 AM   
0 374 By Aram Shahinyan
01 Jul 2014 12:33 AM   
Post Initial condition setup in spectre analog environment
started by rajrevanth61  on 30 Jun 2014 11:37 AM   
0 395 By rajrevanth61
30 Jun 2014 11:37 AM   
Post Can spef file from extractRC contain the pin capacitances?
started by schnufff  on 30 Jun 2014 04:26 AM   
0 376 By schnufff
30 Jun 2014 04:26 AM   

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