Home > Community > Forums > Digital Implementation

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Digital Implementation Forum

Page 1 of 86     12345 ... Last
  Topics   Replies     Views     Last Post  
Post Add space to the top and bottom of standard cells
started by Nga Cao  on Yesterday at 07:47 PM   
0 52 By Nga Cao
Yesterday at 07:47 PM   
Post NRDB-669 Warning
started by Roberto Numony  on 08 Jun 2010 08:34 AM   
2 1170 By ravi ki
10 Sep 2014 12:57 AM   
Post Having trouble reconciling the LEF Tech file with the PDK tech file
started by Bret Howe  on 08 Sep 2014 03:25 PM   
0 429 By Bret Howe
08 Sep 2014 03:25 PM   
Post relxpert vth degradation
started by Shiny  on 29 Aug 2014 12:13 PM   
0 1058 By Shiny
29 Aug 2014 12:13 PM   
Post hold fixing in scan chains
started by chris06  on 28 Aug 2014 09:05 AM   
0 1077 By chris06
28 Aug 2014 09:05 AM   
Post EDI Placement Density Screens Honored after Optimization?
started by Aram Shahinyan  on 01 Jul 2014 12:33 AM   
2 1715 By Aram Shahinyan
20 Aug 2014 03:18 AM   
Post Power Analysis EPS vs. EDI
started by marten  on 18 Aug 2014 05:42 AM   
0 1259 By marten
18 Aug 2014 05:42 AM   
Post Cannot find output terms for clock synthesis
started by FMRLI  on 31 Jul 2014 06:18 AM   
3 1479 By wally1
08 Aug 2014 09:16 AM   
Post Pads on 3D IC
started by Costero  on 31 Jul 2014 02:50 AM   
0 1393 By Costero
31 Jul 2014 02:50 AM   
Post Parasitic Extraction including floating stripes on top metal layer
started by salmancmosis  on 30 Jul 2014 12:53 AM   
0 1370 By salmancmosis
30 Jul 2014 12:53 AM   
Post Litho physical analyser is used to reduce variations in 90 nm and below. What exactly is a hotspot in the context of LPA ?
started by GayathriJ  on 29 Jul 2014 10:24 PM   
0 1378 By GayathriJ
29 Jul 2014 10:24 PM   
Post ELC not using spectre
started by Khenglish  on 23 Jul 2014 02:23 PM   
4 1395 By Khenglish
25 Jul 2014 10:59 AM   
Post ELC cannot run db_spice
started by great ljx  on 23 Jul 2014 08:35 PM   
1 1352 By Khenglish
24 Jul 2014 09:57 AM   
Post ELC (Simulation failed with the status 25600)
started by maple  on 24 Jul 2014 02:03 AM   
0 1331 By maple
24 Jul 2014 02:03 AM   
Post Cadence ELC not recognising SPECTRE format
started by eklikeroomys  on 16 May 2011 03:08 AM   
4 4336 By maple
24 Jul 2014 01:43 AM   
Post script to run IRUN
started by tonio  on 23 Jul 2014 11:52 AM   
0 1316 By tonio
23 Jul 2014 11:52 AM   
Post Import Synthesized Verilog Netlist to Virtuoso
started by gnaw  on 23 Jul 2014 07:40 AM   
0 1327 By gnaw
23 Jul 2014 07:40 AM   
Post IC5141 CDL in skipping passive devices
started by lcaley  on 20 May 2013 01:19 PM   
2 2252 By csst
23 Jul 2014 02:56 AM   
Post Help with designing of NEMS switch in pspice
started by rajrevanth61  on 22 Jul 2014 09:38 AM   
0 1305 By rajrevanth61
22 Jul 2014 09:38 AM   
Post Design partition in soc encounter 10.1
started by FMRLI  on 21 Jul 2014 10:56 AM   
0 1315 By FMRLI
21 Jul 2014 10:56 AM   

Page 1 of 86     12345 ... Last

There are 1582 guest(s) and 2 member(s) online:
Hossein1357

Most Active Users
1. Hossein1357 (152)   

Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.