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Cadence Technology Forums
Forum NameTopicsRepliesLast Post
    Hardware/Software Co-Development, Verification and IntegrationModerator: Frank Schirrmeister219491ViVA bus plot to full view plo ...
By: 3489
17 Apr 2014 01:42 PM
    Functional VerificationModerator: Adam Sherer11753738step simulation
By: sebgimi
18 Apr 2014 06:22 AM
    Functional Verification Shared CodeUpload your code here. Please give a brief summary of how to use it. 54138Re: Specman Mode for Emacs
By: guzman
26 Feb 2014 02:45 PM
    Logic Design Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Noel, Lisa
5371537Re: how to synthesize delay el ...
By: micro469
17 Apr 2014 11:05 PM
    Digital ImplementationDesign Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Noel
16525237Re: REG CADENCE Encounter 90nm ...
By: Kari
18 Apr 2014 08:49 AM
    Custom IC DesignModerator: Andrew Beckett.294412024Re: Change CDF variables from ...
By: Quek
19 Apr 2014 09:00 PM
    Custom IC SKILLModerator: Andrew Beckett.225510184Rewriting the bulk connection ...
By: Vaasu
19 Apr 2014 06:23 AM
    RF DesignModerator: Andrew Beckett.4391751Re: Double Exponential Current ...
By: Andrew Beckett
18 Apr 2014 05:52 AM
    PCB DesignFrom schematic to autorouting what are your challenges in producing high-speed designs?564720735Re: New VIA definition
By: ScottCad
18 Apr 2014 01:57 PM
    PCB SKILLUpload your SKILL files here. Give a brief summary of how to best use the SKILL code.10484286Re: Waive DRCs report
By: Randy R
18 Apr 2014 11:23 AM
    IC Packaging and SiP DesignPackaging solutions can make or break the cost budget. What design issues are you facing today? 101264Re: Who uses System Connectivi ...
By: tonyhuffman
14 Apr 2014 08:09 AM
    High Level SynthesisModerator: Rajesh Radhakrishnan610Re: sc_vector support
By: Roman Popov
09 Jan 2014 09:02 AM
    Mixed-Signal DesignThis Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andreas Lenz
75255Re: invoke modelwriter
By: gnaw
10 Apr 2014 08:10 AM
    RAVEL DRC Programming for IC Packaging and PCBEverything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
511Re: Ravel IDE
By: ztzg
05 Mar 2014 05:48 AM
General Topics
Forum NameTopicsRepliesLast Post
    AnnouncementsNews, FAQs, and related info about how to best use the community.
Moderators: Community Operations
1619Is there a Concept HDL forum?
23 Dec 2013 10:41 AM
    Cadence Academic NetworkFOR ACADEMIC INSTITUTIONS: Share your approaches in design and the use of Cadence tools with fellow students and faculty.
Moderator: Patrick Haspel
120289Re: PSPICE Simulation Error &q ...
By: electron7
28 Mar 2014 12:39 PM
    Feedback, Suggestions, and QuestionsProvide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
196486Re: Licence borrowing
By: oldmouldy
17 Apr 2014 11:18 AM
    JobsPost jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.5357Great Opportunities in EDA, Pl ...
By: epeefencer
11 Feb 2014 06:34 PM

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