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Digital Implementation Community

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	Answers to Top 10 Questions on Performing ECOs in EDI System By Brian Wallace on April 17, 2013 Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately... Read more » Comments (0) Filed under: Cadence EDI System, ECO, Encounter digital Implementation system, LEC, MMMC, synthesis, tips and tricks

	Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis By Kari Summers on March 26, 2013 When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use... Read more » Comments (0) Filed under: bump, EDI, EPS, Five-Minute tutorial, flip chip, power analysis, rail analysis

	CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market? By Vasu Madabushi on March 10, 2013 Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user... Read more » Comments (0) Filed under: AppliedMicro, ARM, ARMv8, Avago, CCOpt, CDNLive, CDNLive Silicon Valley, CDNLive! Cadence, Cortex-A15, Cortex-A57, Cortex-A7, digital, Digital Implementation, EDI, Encounter Digital Implementation, GigaOpt, high performance, low power, NVidia, RC-Physical, SoC

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