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System Development – What To See At DAC 2010

Comments(0)Filed under: ARM, wind river, SystemC, DAC, osci, hls, Calypto, ITRI, TSMC, Cadence, Gary Smith, System Realization, DAC 2010, Imperas

The EDA360 vision paper specifies key System Realization challenges. Embedded software development and verification are rapidly becoming the key increasing cost factors for the electronics industry. Integration and re-use are becoming critical for the success of any electronic company. In this blog, I will summarize the specific system development discussions, presentations and demos that Cadence and its collaboration partners will provide during the upcoming Design Automation Conference (DAC) along with other system-level activities that will be held during the show. If you are a system, software, algorithm, or verification engineer, or a designer who is migrating into a higher level of abstraction, I am sure you will find this information to be useful.

This year, Cadence will have four key activities on the exhibit floor around its booth (Hall B #1334):

1.       Suite presentations - These presentations will provide you a good overview about the specific solutions that Cadence provides to address specific challenges. A combination of presentations and demos that covers Cadence solutions for System Realization challenges will be covered within the following session: System Development with Scalable Performance, Improved Productivity and HW/SW Integration. We will present this overview several times a day on Monday (June 14) through Wednesday (June 16).  I recommend that you register (using the above link) to a specific slot prior to the show.

2.       Pod areas at the booth - Learn more about EDA360 by attending one of Cadence pods. Each pod will have a high-level overview about one of the EDA360 components (System Realization, SoC Realization and Silicon Realization) and a complimentary set of demos provided by Cadence technical experts. The System Realization pod (look for the Palladium XP Verification Computing Platform) will offer a combination of live and video demos including:

     a. Palladium XP Introduction video demo

     b. ARM VSTREAM video demo 

     c. Cadence/Wind River Simics demo

     d. HW/SW co-debug with ARM based design 

     e. Metric Driven Verification for acceleration

3.       Cadence theater is located just across the booth. Learn from experience of Cadence customers and partners how other companies use or collaborate with Cadence solutions, methodologies and flows in order to reduce the cost of development and increase productivity and profitability. I will cover the specific topics and presenters on the day to day agenda below.

4.       Private meetings - if you are interested in meeting with Cadence system design and verification management or technical experts, please contact me through email at ran@cadence.com and I will help you coordinate the meeting.

Cadence will also have a presence at the TSMC booth (Hall C booth #294), ChipEstimate.com (covering chip planning solutions) at Hall C booth #521, and OVM World/UVM World at Hall B booth #1350.

See below for day by day activities.

Friday - June 11

There is a small IEEE International event called High Level Design Validation and Test (HLDVT) Workshop 2010 at the Anaheim Convention Center. This event is co-located with DAC 2010.  The workshop focuses on addressing the current bottlenecks in validation and test of complex and heterogeneous systems by both employing high-level specifications and developing associated tools, techniques and methodologies to enable drastic reductions in the overall design, validation and test effort. Session 6 (4:25pm) is going to focus on test and debug and specifically emulation, with presentations from Mentor, Cadence, IBM and a speaker from academia.

Sunday - June 13

There are three events I would like to highlight:

1.       The 13th North America SystemC User Group Meeting from 2:30-6pm at the Anaheim Hilton California Ballroom A. New videos include a keynote from Michael (Mac) McNamara about the synthesizable subset of SystemC.

2.       The EDA Consortium and the DAC Executive Committee will get things going with a Kick-Off Reception Sunday at 6:00 pm at the Hilton. I like to go to this event, which has been for many years the opening for DAC and an opportunity to meet your friends from the industry. The sponsorship this year comes from user companies including ARM, Intel, NVidia, Qualcomm, and STMicroelectronics.

3.       Right after the reception, at Ballroom A at 7:30pm Gary Smith and Mary Olson will provide an annual update on the state of EDA including trends and forecasts.

Monday - June 14

1.       If you did not attend the update from Gary Smith on Sunday evening, you will have the opportunity to hear Gary on a Monday morning Pavilion Panel on "What's Hot at DAC."

2.       A full day (9am-5pm) DAC co-located event organized by the European Electronic Chips and Systems Design Initiative (ECSI) is called: "Choosing Advanced Verification Methods: So Many Possibilities, So Little Time."  Brian Bailey will provide the keynote speech and a combination of EDA verification vendors and customers will cover different verification topics. Mike Stellfox (from Cadence) will facilitate the verification planning topic with focus on ESL. J.C. Yeh from the Industrial Technology Research Institute (ITRI) of Taiwan will present ITRI experiences with the Cadence solution.

3.       Cadence theater system presentations:

     a. Simon Davidmann, President & CEO of Imperas Software Limited will present at 2:30pm "Imperas and Cadence: Breaking New Ground in Embedded Software Verification"

     b. Stan Krolikowski, OSCI board member and officer, will present at 2pm "OSCI standards-based update"

     c. Tom Sandoval, CEO of Calypto Design Systems, will present at 3:00pm on "Next Generation EDA"

4.       Other Cadence demos and suite presentations, as were mentioned above.

Tuesday - June 15

1.       Management day sponsored by Cadence runs from 10:30 to 6pm at the convention center room 204C. Within this day, there is an interesting session covering the topic "Decision Making for Complex ICs" including panelists from PMC-Sierra, TI and AMCC. 

2.       Cadence theater system presentations:

     a. Michel Genard, Vice President of Product Strategy and Marketing at Wind River Simics will present at 11:30 "Helping the EDA360 System Realization Vision Become Reality"

     b. Vincent.Korstanje, Director of Technical Marketing for System Design tools at ARM, will present at 2pm "Moving towards EDA360 with ARM/Cadence System Realization Collaboration"

     c.  Ashok Mehta, a verification manager from TSMC, will present at 4:30pm "TSMC Open Innovation Platform (OIP) ESL Enablement Flow with Cadence"

3.       Other Cadence demos and suite presentations as were mentioned above.

Wednesday - June 16  

1.       User track poster session on 1:30pm at 2nd Floor Foyer Adjacent to 208AB. This is the second User Track poster session at DAC. Join us in viewing approximately 40 posters including a case study involving an OVM-based ESL verification flow by Jen-Chieh Yeh from ITRI

2.       Cadence theater system presentations:

     a. Brian Bailey will present at 10am on "Functional Virtual Prototypes as part of ESL flow"

     b. Simon Davidmann, President & CEO of Imperas Software Limited will present at 11am "Imperas and Cadence: Breaking New Ground in Embedded Software Verification"

     c. Vincent.Korstanje, Director of Technical Marketing for System Design tools at ARM,  will present at 2pm "Moving towards EDA360 with ARM/Cadence System Realization Collaboration"

3.       Other Cadence demos and suite presentations as were mentioned above

Thursday - June 17

1.       Embedded SoC enablement day runs from 9am to 6pm at the convention center room 303A:

     a.  An interesting session from 9am to 11am will cover the topic "Enabling tomorrow's complex SoC" with participants from Intel, Virage Logic and Cadence.

     b.  The session "Trade-Offs and Choices for Embedded Solutions" will discuss SoC development trade-offs with participants from MontaVista, Xilinx, TSMC and ARM.      

2.       User Track Poster Session at room 208AB from 4:30pm to 6pm including:

Developing Synthesizable IP Modules from TLM 2.0 Descriptions - A Methodology Case Study
By: Christian Sauer & Felice Balarin, Cadence Design Systems

3.       Panel - What Input Language is the Best Choice for High-Level Synthesis (HLS)?  - at room 207AB from 4:30pm to 6pm. Speakers at this panel are from Cadence, Forte, Synfora, Mentor and Calypto.

The above listings represent a fraction of the events on the DAC conference program. A complete program listing can be found on the DAC web site, as can registration information. The Cadence DAC web site lists Cadence activities. I hope to see you at DAC 2010. If you have any questions in related to the above, I will be happy to respond.  

Ran Avinun



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