	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the System Design and Verification blog (individual posts).

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

System Design and Verification Blog

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform By Jason Andrews on May 24, 2012 There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical... Read More » Comments (0) Filed under: embedded software, QEMU, linux, SystemC, System Design and Verification, virtual platforms, virtual prototypes, Virtual System Platform, Xilinx, Zync-7000, USB, physical USB devices

How Debug Breakthroughs are Enabled by In-Circuit Acceleration By Frank Schirrmeister on May 16, 2012 We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit... Read More » Comments (0) Filed under: Acceleration, Emulation, Incisive, functional verification, DAC, System Design and Verification, CDNLive, debug, System Development Suite, Palladium XP, Design Automation Conference, in-circuit emulation, In-circuit acceleration, AMD, DAC breakfast

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On! By Frank Schirrmeister on May 14, 2012 I think all of us engineers have faced at one point or another the need to explain to our parents or friends what we are actually working on. Hey Mom, EDA is where electronics begins! Without us electronics would not change our day to day lives ... Punctually... Read More » Comments (0) Filed under: Incisive, System Design and Verification, virtual platforms, virtual prototypes, System Development Suite, Virtual System Platform, VSP, Palladium XP, Watson, FPGA-based prototyping, Mother's Day, Jeopardy, Rapid Protoytping Platform, cloud computing, American Technology Awards, Raritan, awards

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox By Jason Andrews on May 7, 2012 In my last blog post , I covered three frequently asked questions about using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox appliance. Today, I'll cover the next most frequently asked question. It is related to simulation performance. This... Read More » Comments (0) Filed under: ESL, embedded software, linux, virtual prototype, System Design and Verification, Ubuntu, Virtual Machine, virtual platforms, graphics, simulation, System Development Suite, VSP, Xilinx, VirtualBox, Zynq-7000, taskset, Linux vs VirtualBox, Unity3D, Unity 2D

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition By Jason Andrews on May 2, 2012 The use of virtual machine technology offers great ease of use benefits. Since the virtual platform for the Xilinx Zynq-7000 Extensible Processing Platform has been available as a virtual machine appliance, I have seen it run by many people who would... Read More » Comments (0) Filed under: ESL, embedded software, System Design & Verification, Ubuntu, Virtual Machine, virtual platforms, virtual prototypes, system design, Xilinx, VirtualBox, Zynq-7000, FAQ, Xilinx SDK, NAT, Zynq virtual platform, port forwarding, VBoxManage, network address translation, Eclipse

Modeling Large Memories in SystemC By Jason Andrews on April 13, 2012 Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as... Read More » Comments (2) Filed under: Verilog, linux, SystemC, TLM, virtual platforms, Memory, virtual prototypes, Zynq, SystemC memories, SDRAM, memory models, modeling memories

Trying to Make Sense of the Chaos – Impressions from Design West 2012 By Frank Schirrmeister on April 3, 2012 Walking the show floor of "Design West," the show formerly known as "Embedded Systems Conference," I was as confused as ever. This was the most diverse exhibition I have ever been to. The 222 exhibitors varied from vendors offering... Read More » Comments (0) Filed under: Intel, embedded software, ARM, software, UML, Design West, test, SysML, operating systems, Embedded Systems Conferences, embedded systems, software development tools, OS, chaos

Differentiation Through Hardware is Not Going Away By Jack Erickson on March 5, 2012 Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that... Read More » Comments (0) Filed under: High-Level Synthesis, SystemC, TLM, hardware-dependent software, android, SoC, software, 4G, DVCon, System Realization, smartphones, hardware, sub-systems, tablets, Quad-HD, iOS

Virtual Divide and Conquer Enables Fixed Sub-Systems By Frank Schirrmeister on February 23, 2012 The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level... Read More » Comments (0) Filed under: verification, SystemC, TLM, FPGA, System Design and Verification, NASCUG, DVCon, virtual platforms, virtual prototypes, IP, Tensilica, Zynq, Xilinx, sub-systems, subsystems, fixed sub-systems, platform, OMAP

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000 EPP By Jason Andrews on February 21, 2012 Linaro has emerged as a great place to find well tested toolchains, Linux kernels, and evaluation builds for Ubuntu and Android . Everything is focused on the ARM Architecture which is great news for me since almost all of the projects I work on also... Read More » Comments (0)

View older posts »

Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

Popular Tags

Share

Subscribe

Contact Us

System Design and Verification Blog