The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
By Jack Erickson
on May 14, 2013
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing....
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Filed under: ASIC, C, C++, C-to-Silicon Compiler, DAC, High-Level Synthesis, hls, Internet, microcontroller, microcontrollers, microprocessors, processors, programmable world, SystemC, the internet of things, TLM, TLM 2.0
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Creating Virtual Platform Models
By Jason Andrews
on April 29, 2013
One of the most common questions asked about virtual platforms is: Who creates the models? There are many sources of models and there are people who can make additional models (like Cadence), but obtaining some experience in model creation and virtual...
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Filed under: Cadence, Cadence Virtual System Platform, Model creation, System Design and Verifcation, SystemC, SystemC modeling, timgen, TLM, TLM 2.0, TLM-2, TLM-2.0, virtual platform models, virtual platforms, virtual prototoypes, VSP Log Viewer
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What to See at the DATE Conference: High-Level Synthesis
By Jack Erickson
on March 14, 2013
The DATE (Design Automation and Test in Europe) Conference is next week (March 18-22, 2013) in Grenoble, France. If you are lucky enough to be in Grenoble at this time of year, it will be worth it to check out Session 11.2 "High-Level Synthesis and...
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Filed under: Alex Kondratyev, C-to-Silicon Compiler, DATE, ESL, High-Level Synthesis, hls, QoR, System Design and Verification, system-level
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System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
By Frank Schirrmeister
on March 8, 2013
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December...
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Filed under: Accelerated Verification IP, Acceleration, AMD, ARM, AVIP, Bluespec, Cadence, CDNLive, CDNLive!, dynamic power analysis, embedded software, Emulation, Fast Models, Freescael, Imperas, Incisive, Intel, low power, low power optimization, Palladium XP, PXP, RPP, Samsung, Schirrmeister, System Design and Verification, System Development Suite, System to Silicon Verification, Teledyne LeCroy FPGA Based Prototyping, VCP, Verification Computing Platform, Verification IP, Virtual System Platform, VSP
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Securing Invisible Things … or “Why Denial Works!”
By Frank Schirrmeister
on February 27, 2013
The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices...
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Filed under: Acceleration, ADAS, ARM, Automotive, Cadence, Cylance, Driver Assist, DVCon, embedded software, Embedded World, Emulation, Error Injection, FPGA Based Prototyping, functional verification, Hacking Exposed, McClure, Palladium XP, Safety, Schirrmeister, Security, System Design and Verification, System Development Suite, Testing, verification, Verification Computing Platform, Virtual System Platform, Vulnerabilities
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Application Specific System-Design and Verification at Embedded World and DVCon
By Frank Schirrmeister
on February 25, 2013
This week (February 25 th 2013) is a busy one for system development and the Cadence System Development Suite in particular. For mobility, the place to be is Barcelona -- the Mobile World Congress will show the latest in everything mobile and connected...
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Filed under: applications, application-specific, apps, automotive electronics, DVCon, embedded software, embedded systems, Embedded World, hardware/software, Internet of Things, Mobile World Congress, Nuremberg, Schirrmeister, software, software development, System Design and Verification, System Development Suite, virtual platforms, virtual prototypes
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Embedded World 2013: Virtual Platforms Connected to Everything
By Jason Andrews
on February 22, 2013
Sometimes it is hard to explain why certain ideas take off and why others don’t. There are many stories of poor products that are more successful than much better products. There are also many stories about products that struggle in one time or...
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Filed under: embedded software, Embedded World, embedded world conference, Emulation, linux, Palladium XP, Rapid Prototyping Platform, RPP, simulation, system design, System Design & Verification, virtual platforms, virtual prototyping, Virtual System Platform, VSP
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What the 787 Dreamliner Can Teach Us About SoC design
By Jack Erickson
on February 20, 2013
The commercial aircraft industry is at a stage where it innovates at a much slower pace than the chip design industry -- however, we can find some parallels that offer us lessons. The most notably innovative aircraft recently developed is the Boeing 787...
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Filed under: 787, 787 Dreamliner, Apple, Apple A6, Boeing, C-to-Silcon, Dreamliner, fire, Harvard Business Review, IP assembly, iPhone, Jay-Z, outsourcing, SoC, SoC design, system design, System Design and Verification, SystemC, TLM
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Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along
By Jack Erickson
on February 14, 2013
Recently one of our competitors issued a press release claiming to be the first high-level synthesis (HLS) vendor to support IEEE 1666 TM -2011 SystemC. Specifically mentioned was newly-added support for asynchronous resets in SC_THREADs. Congratulations...
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Filed under: asynchronous reset, C-to-Silicon Compiler, IEEE 1666-2011, Incisive, QoR, SystemC
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A Concrete Linux Virtual Platform Example
By Jason Andrews
on January 25, 2013
Virtual platforms are used to find many different types of system and software issues. Of course, platforms take some time to develop and debug (regardless of what you read in marketing brochures), but in most situations the benefits outweigh the time...
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Filed under: debugging software, Device Drivers, embedded software, Jason Andrews, linux, softtware bugs, System Design and Verification, SystemC, UART, Ubuntu, virtual platforms, virtual prototypes, Xilinx, Zynq, Zynq virtual platform, Zynq-7000
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