RF Design

Going broadside with electromagnetic modeling of advanced processes

TomC — Thu, 09 Oct 2008 13:30:00 GMT

It has caught my attention that designs using fabrication processes such as 65nm, 45nm, 32nm, and smaller, have changed the landscape when it comes to electromagnetic (EM) modeling of components and interconnects. These designs have to contend with the...(read more)

Tip of the Week: When should I use the pss/qpss Harmonic Balance vs. Shooting Newton Engine?

Tawna — Wed, 03 Sep 2008 12:02:00 GMT

Shooting Newton (shooting) and harmonic balance (HB) are complementary technologies and used for circuits that exhibit different behaviors. The shooting Newton algorithm uses an adaptive time step control, which is particularly effective for sharp transitions...(read more)

Tip of the Week: Guidelines for simulating oscillators - phase noise simulations

Tawna — Tue, 26 Aug 2008 15:07:00 GMT

When simulating oscillators, it is important to choose the correct simulator engine (shooting Newton vs. harmonic balance.) In general, we suggest that you use the HB (harmonic balance) engine as your first choice. In addition, there are situations where...(read more)

Tip of the Week: New nport parameter ( dcextrap ) for modeling longer transmission lines

Tawna — Mon, 18 Aug 2008 18:21:00 GMT

There is a new nport parameter, dcextrap, available in MMSIM 6.2.1. The values are constant or unwrap. The default is constant. dcextrap is typically used when the nport s-parameter data file models a system with long delay – and -- the DC point...(read more)

Simulating MOS Transistor ft

Art3 — Sat, 09 Aug 2008 07:25:00 GMT

One other question that you might ask is, this approach works for bipolars but what happens when you need to characterize a MOS transistor. Nothing changes, use the same testbench and measurements, see figure 1. In this testbench a MOS transistor is being...(read more)

Tip Of the Week: analogLib mtline now has a cross sectional viewer when Type of Input=Field Solver

Tawna — Mon, 04 Aug 2008 18:10:00 GMT

Many users have indicated that it is challenging to correctly enter complex transmission lines (multiple conductors, conductors at different heights, and multiple dielectrics) into the analogLib mtline when using the Field Solver Type of Input. You wanted...(read more)

Tip of the Week: Why Do Shooting and Harmonic Balance Phase Noise Results Differ?

Tawna — Tue, 29 Jul 2008 15:12:00 GMT

Question: You are simulating your VCO in SpectreRF. You ran your PSS + Pnoise (noisetype=sources) simulations using the Shooting engine pss+pnoise and plotted the phase noise. You noticed that the SpectreRF phase noise results differ significantly for...(read more)

Tip of the Week: Please explain in more practical (less theoretical) terms the concept of "oscillator line width."

Tawna — Fri, 25 Jul 2008 22:45:00 GMT

Question: From spectre -h pnoise. I find the definition for oscillator linewidth: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ " In a phase noise analysis for an oscillator, the line width, which is also known as the corner frequency...(read more)

Measuring Transistor ft

Art3 — Wed, 16 Jul 2008 13:30:00 GMT

So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A couple of questions to consider before starting are:

What parameters do you want to measure?
What types of test benches are required to measure these parameters?

Let’s start by considering how to measure the ft of a transistor, ft is a standard figure of merit used by analog designers to evaluate a transistor’s performance. Later we will consider how to measure some other common transistor parameters fmax, Noise Figure, as well as, measuring device stability.

First, let’s review the meaning of ft. It is defined as the unity gain frequency of a transistor’s short circuit current gain. The first point is that we need to measure the short circuit current gain so ideally the output terminal, collector [drain] of the transistor will be connected to a power supply. The next point is that we need to calculate the current gain of the transistor. For Virtuoso Analog Design Environment users, the Virtuoso Visualization and Analysis waveform calculator can be used to perform this measurement. To calculate ft, plot the current gain by dividing the collector [drain] current by the base [gate] current and then using the cross function to find the unity gain frequency. An example of calculating ft, is shown in Figure 1.

Figure 1: Measuring Transistor f_t

When creating a simulation test bench the natural place to start is the actual measurement test bench. To measure ft, an RF network analyzer can be used to measure the s-parameters and then the s-parameters can be converted into h-parameters. By plotting the h21, the ft can be estimated by extrapolating the unity gain frequency of the h21. This approach works well in the lab because wideband shorts do not exist in the real world. So RF measurements need to be performed with input and output matching and a result s-parameters are the natural method for characterizing transistors. One issue when testing in the lab is the need to for separate bias and RF sources. Typically these sources are isolated with a bias T. In place of a bias T, we will use an inductor [pass the bias voltage at dc] and a capacitor [pass the RF input at frequency].

Figure 2: Emulating the Network Analyzer Setup to Measure h21

Using the lab test bench introduces some complexity that is not required when performing the measurement in simulation. By taking advantage of the “ideal” nature simulation, the test bench can be simplified. In simulation, we can create a perfect short using a voltage source. The voltage source provides bias and acts as a short circuit replacing the output matching circuitry in the original test bench. The RF input has been replaced by a current source with ac magnitude of 1 so the current gain can be directly measured. The input bias is still controlled by setting a dc voltage, see
Figure 3. This test bench works well when measuring ft for a single bias condition. However, it is difficult to sweep the bias current of the transistor as can be done in the lab with a bias generator.

Figure 3: Enhanced Test bench with an Output Short

The next enhancement is to replace the bias voltage source and resistor with a diode connected transistor and a current source to set the bias current of the device under test [DUT], see Figure 4. Using a diode connected transistor to generate the bias voltage allows the bias current to be easily controlled. The dc bias and the RF input are still isolated by the pseudo bias T. This change to the test bench allows a designer to characterize the effect of bias current on ft so the transistor can be operated at its maximum ft.

Figure 4: Improved ft Testbench

Another enhancement to the test bench would be to replace the inductor and the capacitor used in the pseudo bias-T, shown in Figure 5. Virtuoso Spectre simulator provides users analysis dependent switches that can be set to open and closed depending on the analysis to be performed. This allows the designer to use the same test bench to perform multiple tests, for example, NF, fmax, etc.

Figure 5: Using analysis dependent switches

The test bench I use to measure ft is even simpler, the the bias network [diode, analysis dependent switches, and RF source] is replaced by an ideal current mirror. The current mirror provides feedback to stabilize the bias point. The current source that sets the bias current is also RF input source the bias T is eliminated. BTW, you might recognize this type of circuit, it is called a Wilson current mirror, shown in Figure 6.

Figure 6: My ft Test bench
To review the test bench development process, we started by replicating the test bench we used in the lab in simulation. Then the test bench was optimized by tuning it to take advantage the “ideal” nature of a SPICE simulator. Along the way we made several improvement to the measurements process.
1) Directly measured the ft, eliminating the need to generate the s-parameters and then calculate the h-parameters.
2) Added the ability to sweep the bias current so plots of ft vs. Ic can be generated, see Figure 7.

Figure 7: Plot of ft vs. Ic

In closing, I hope that this example of creating a test bench and making measurements will be useful for you. Please let me know what you think.

Best Regards,
Art Schaldenbrand

Inductors On Demand, at least one RF design task can be really automated!

Hany — Mon, 14 Jul 2008 02:52:00 GMT

Inductors, transformers and transmission lines are critical components in any high frequency integrated circuit. Conventional electromagnetic tools used for the design of these components are difficult to setup, require electromagnetic expertise and are not integrated in IC design flows.

Traditionally, specialized modeling teams work hard for several months to design, fabricate and characterize a limited set of inductors and transformers for IC designers to choose from. They repeat this long and cumbersome procedure every time a new process node or a new design application is introduced, adding months to the overall design cycle. IC designers faced by a small selection of passive components and limited analysis capabilities are forced to over design wasting expensive Silicon area and increasing failure rates.

Virtuoso Passive Component Designer is a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. Tightly integrated with Virtuoso Schematic Editor and Virtuoso Layout Suite, the tool brings passive component design to the hands of analog and RF designers.

Starting from design specifications such as inductance, quality factor and frequency, designers can use Virtuoso PCD to automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area. A built-in accurate 3D full wave solver is used to verify the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turn-around-time.

Virtuoso PCD is easy to use and does not require electromagnetic expertise. The output is a complete PDK component with a symbol, schematic, layout and a simulation model. The built-in modeling capability converts S-parameter files into physical lumped element models, ready for RF analysis using Virtuoso Spectre Simulator XL and GXL. Virtuoso PCD also includes a fast and accurate coupling analysis capability enabling designers to optimize the placement of inductors and transformers on the layout resulting in smaller Silicon area and higher yield.

Learn more about Virtuoso Passive Component Designer at:

Senrinotabi

Art3 — Sat, 12 Jul 2008 04:54:00 GMT

Greetings! My name is Art Schaldenbrand and I have been at Cadence for 12 years supporting the custom IC design tools in the Virtuoso platform. My interests tend to be as widely varied as the customers I work with, ranging from Wireless Design to CMOS Image Sensor design and Power Management design.

One common theme that comes up when talking to customers about any aspect of design is the challenge of using simulation to understand their design, from creating testbenches to measuring circuit parameters.

In subsequent appends, I would like to discuss these issues and share ideas with you about how to use simulation more effectively.

- Art

Cadence, the new kid on the Electromagnetic Solver Block

Kabir — Fri, 11 Jul 2008 15:57:00 GMT

On June 16 2008, Cadence introduced a new Electromagnetic (EM) solver technology to address the challenges of verifying wireless integrated circuits implemented in advanced CMOS process nodes. You can read the press release here.

How is this going to help the RF designer? Virtuoso® RF Designer brings a fast planar 3D EM solver to the designer's desktop. With its NlogN speed (where N is the number of unknowns), higher capacity, parallel and adaptive frequency sweep, and tighter integration inside the Cadence Virtuoso® environment, Virtuoso RF Designer makes EM simulation an integral part of the RF IC design flow, as opposed to a stand-alone step.

Virtuoso RF Designer integrates seamlessly into the Virtuoso front-end and leverages Cadence's patented electromagnetic analysis technology to accelerate and accommodate large designs found in today's RFICs, PCBs, and SiPs. It's accuracy has been benchmarked over the last several years by comparing with measurement data from TSMC, IBM, Jazz, and other captive foundries.

Questions or comments? Let me know!