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IC Packaging and SiP Blog

Have a Complex, Off-Grid Pin Pattern to Number? Cadence Allegro16.6 IC Package Design Tools Have You Covered!

Normal 0 false false false EN-US X-NONE X-NONE Complex dies with a mixture of digital and analog circuitry means equally complex pin patterns. Those analog areas often have pins that aren't lined up in nice, straight rows and columns. But, that doesn't...  Read More »
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Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting Via Arrays

Manufacturability and quality of the power and ground feeds for your package are always a big concern for all of us. When you have multiple plane layers, connecting them together with reinforcing vias is a great idea, with just one problem: how do you...  Read More »
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Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence 16.6 IC Packaging Tools

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex substrate - the ability to efficiently fan out the pins in the fewest possible layers is paramount. Get this wrong, and you could end up needing additional layers...  Read More »
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Add a View of Your Package Substrate in Your IC Layout Tool for Maximum Design Context with Cadence 16.6 SiP Layout

We have all heard about co-design, how it is going to get us to market on time, reduce our layer counts, and give us the ability to trade off design decisions at different layers of the system substrates. If you're reading this blog, you almost certainly...  Read More »
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OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as signal and...  Read More »
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Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here . Track 6, the IC Packaging/SI, PI featured customer papers on co-design as well...  Read More »
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Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging Layout Tools

To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that with...  Read More »
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Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout Editors

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility that allows them to extend and modify the tool to meet their specific requirements. This might mean custom SKILL tools developed in-house, scripts/macros to automate...  Read More »
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Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD and SiP Layout Tool

In this week's discussion, let's take a look at a cornerstone of every good substrate design: plane shapes and voiding. In particular, what do you do if you need to void around an object on one or more layers of the object itself, whether a cline...  Read More »
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See the Differences Between Your Designs Visually with the Layer Compare Toolset in 16.6 APD and SiP Layout Tools

Have you ever wondered exactly what has changed between two different versions of a package substrate? Perhaps you've wanted to see exactly what metal on the top surface of your package is exposed through the combination of solder mask openings and...  Read More »
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