PCB Design

What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to See!

Jerry GenPart — Tue, 22 May 2012 18:51:00 GMT

Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16.0, bond wires were implemented as true 3-dimensional objects in the database, and their CV were set according to their profiles.

The 16.5 release has made improvements to increase the designer’s efficiency in setting the CV attributes.

Read on for more details …

Setting the wire profile visibility in Visibility tab

With the new profile-based model, users are able to set the wire visibility in the Visibility tab. The following snapshots portray the Color form and the corresponding Visibility tab that lists wire profiles:

The list of profiles starts after the last displayed layer. The profile list is the same as that in the Color form (i.e. the profiles in the database are listed in alphabetical order). If there are no profiles, nothing is listed after the layer list. The visibility tab is scrollable such that if there are a lot of profiles to be listed, they can all be accessed through the scroll bar. The workings of the check-boxes are the same as those for the layers - the result of setting or unsetting visibility is seen directly on the canvas. There is also a check-box at the top of the profile to quickly set or unset the visibility of all profiles.

Eliminate WIRE subclass visibility setting

Since 16.0, users have found indirect ways to affect the visibility of wires without going through the profile interface. In 16.5, we made the following changes in various areas of the tool:

Hide the WIRE subclass check-box in the Color form and the Color command form so that users cannot directly manipulate the visibility of this subclass.
Ensure that changes in WIRE subclass visibility from other applications get reflected to the profile visibility as well.

Setting Wire DRC visibility in Visibility tab

You can now set the visibility setting of the Wire DRC directly in the Visibility tab. This check-box is similar to the one in the Color Form:

Being able to toggle this check-box in the Visibility tab allows for faster access to display or undisplay Wire DRCs in the canvas; toggling it OFF (background color) will undisplay all the Wire DRC markers (regardless of profiles), and toggling it ON (with the selected Wire DRC color) will show all those markers.

I look forward to your comments.

Jerry "GenPart" Grzenia

What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!

Jerry GenPart — Tue, 15 May 2012 15:05:00 GMT

The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow. These flows provide the benefit of both a guided flow and the simplicity of a default flow.

The 2 Point Flow:

Provides the benefits of a default flow - no path between the gather points
Provides the guidance that is needed - liberty to exit in the direction of choice

For example, if you wish to provide 'no' guidance to some bundles, let the router pick the best path for all the members. So, you route the bundle spatially. Suppose you don't like the way the route exited the component. You wanted it to exit north instead of west as it chose to. Change the bundle's properties to be 'Guided', and place the gather points at the appropriate exit locations. Run the router again and you should see the routes exit the component in the desired direction, yet still be able to route on their own in between the gather points.

Read on for more details …

In GRE, click the RMB on the bundle and select Bundle Properties > General:

You can watch a video of this capability available on Cadence Online Support.

Plan Spatial when Guide Router is OFF:

Plan Spatial when Guide Router is ON:

Please share your experiences using this capability.

Jerry "GenPart" Grzenia

What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements!

Jerry GenPart — Tue, 08 May 2012 18:51:00 GMT

More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router.

Read on for more details…

In this release, the SPECCTRA auto-router provides the ability to use inset/tangency and stagger via patterns.

Autorouting with Via Patterns

The auto-router takes into consideration effective inset/tangency rules to find the most optimal 3D path. Usage of via patterns is regulated by via and via pattern costs.

Ordered Via Lists

In Allegro PCB Editor, the via lists were prioritized, but prior to the 16.5 release, the Allegro PCB Router did not have this capability. The 16.5 release now provides this ability.

This command will turn on/off the prioritization of the via list provided by Allegro.

set follow_usevia_priority on/off

Note: It is best to set this switch to on ONLY when working with HDI structures. When using standard PCB structures it is preferred to NOT set this switch.

Anti-acid bars

To avoid the acid traps at tangent/inset bbvias/microvias, Allegro PCB Router allows the creation of anti acid bars. These are rectangular bars created on each layer to avoid the acid traps.

The anti-acid bars are created by using the following command:
create_anti_acid_bar

This command may be used to remove the anti-acid bars
remove_anti_acid_bars

The Allegro PCB Router constructs an anti-acid bar for each pair of tangent/inset bbvias as a path on a shared layer with the valid width values:

I welcome your feedback on these new 16.5 capabilities.

Jerry “GenPart” Grzenia

Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin

TeamAllegro — Tue, 08 May 2012 15:54:00 GMT

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson. Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second. And if that was not enough, he then went into an in-depth description of why power delivery network (PDN) analysis is required. The room was packed with engineers getting a great two day education.

After two days of classroom academics, the students then were offered a third day of free education which featured hands-on experience using Cadence Allegro signal and power integrity tools. In the morning of the third day, the students were able to run extensive signal integrity analysis on a DDR memory system as well as high speed serial links using IBIS-AMI models to drive the multi-gigabit interfaces. In the afternoon, the students focused on using the Allegro PDN analysis technology which allows for power integrity checks directly from the design database without the need for translation.

A number of students commented that Robert Hanson’s teaching and experience included good background and valuable historical data. They enjoyed his presentation style and interaction with students which resulted in a valuable two days of classroom education. And the bonus of being able to take the classroom education into the lab and actually run the Cadence signal and power integrity tools made the experience even more valuable.

If you were one of the lucky ones that were able to take advantage of this three day event, please give us your comments below. If you are interested in learning more about Allegro PCB SI or PDN analysis tools, please click here.

TeamAllegro

What's Good About Allegro Via Patterns During Group Routing? See for Yourself in 16.5!

Jerry GenPart — Mon, 30 Apr 2012 18:13:00 GMT

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing.

Group Routing Review

The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing a bus with traces that follow the same path and have common physical and electrical rules. To specify the nets for group routing, select the elements (such as clines, pins, vias, and ratsnests) from which to route either by using the Temp Group option from the add connect pop-up menu, or selecting the elements with a window. Routing proceeds from the selected elements.

Note: You can initiate a route by selecting ratsnest lines provided that you have enabled Ratsnests in the Find Filter. To reduce the incidence of accidental ratsnest selection, the editor ignores the ratsnests if you also select other types of elements.
Note: If you are routing from a component with a complicated pin pattern, route from each pin to a location outside the component area. Then group the routes together (outside the component area) in the order that you want to route them as a group -- that is, organize the routes outside the component area so that the layout editor can order and space them properly.

Read on for more details …

Via Pattern Support

Via pattern support during group routing is available when you are in the add connect command. You can add vias during group routing in both the modes-Alternate mode and Working layer mode. With the Alternate use-model enabled, you can select the via from the Options tab. With the Working Layer use-model enabled, you can pick the target-layer from the Add-Via dialog box. For adding vias in group routing, the same padstack (or via-stack) is used for all selected clines, and is determined by the control-trace. A DRC may appear if a padstack is invalid for one or more of the selected clines.

Adding Via Patterns during Group Routing

Select the add connect command using Route — Connect and create group to add vias. In the following figure four cline segments are selected. The control-trace is shown by the white X:

Now select via-pattern from pop-up menu and add the via by double clicking the cline segments. The vias remain in the floating state until one additional click is made. New clines will gather, and then group route continues on the new layer. The via-pattern is created, and all the vias will slide dynamically as a group in the direction of the control-trace. The control-trace via is placed directly along the control-trace cline, with no extra vertices added. Extra vertices are added for the other traces if needed.

Types of Via Patterns

There are six type of via patterns. You can select the via pattern from pop-up menu. The Next Pattern option can be used to cycle to the next via pattern in the list:

The shape of the via-pattern can change depending on which cline is the control-trace. To change the control-trace use the pop-up menu. Taper patterns produces the same result as one of the diagonal patterns if the control-trace is at the either of the end. If the vias are small, and/or the selected clines are already far enough apart, in group routing vias are added in-line, with no extra vertices.

Adding Stacked Blind/Buried Vias During Group Routing

For designs using stacked vias, you can select only those layers that can be reached with a single via-stack. The layers that can only be reached with staggered vias cannot be selected for adding vias in group routing. The example in the following figure shows three via-stacks (labeled "1-3"). You can add stacked vias during group routing by invoking the command once:

If via-stacking is not allowed on layer three, then in order to add the vias from layers 3-to-6 you need to select add via second time, with layer six as the target layer. You can move vias labeled "3:6" vertically up or down until you click to drop them. To avoid any DRCs with the "1-3" via-stacks the "3:6" vias are placed in staggered form.

Please share your experiences using this new 16.5 capability.

Jerry “GenPart” Grzenia

What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

Jerry GenPart — Mon, 23 Apr 2012 17:50:00 GMT

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command.

Read on for more details…

After you execute the Find command on a design, you can generate a report (in CSV or HTML format) for the results from the Find command. If you run the Find command to search for different types of objects in a design, the search results will display in different tabs of the Find window. In this case, you can export the data from each tab. In 16.3 Capture CIS version, you could only export results from the Find report in HTML format, not in CSV format.

Steps:
1. Open any design. Select Project Manager > highlight .dsn > search for all parts in search/find window (as shown below):

2. Make sure that you have selected multiple objects so that result would have different tabs. Hit the return key to get the results as shown below:

3. Select any tab (say Parts-Pin) > highlight any row > Right Mouse Button Click > Save as CSV.

4. You will receive the message “INFO (ORCAP-1193): CSV file saved at design_file_location” as shown above.

Here’s the content of the “-PARTS PINS(Logical)-Report.csv” which is present at design location:

Note: The report does not open when you run the command. You need to go to the specified location and open the report in the associated application.

Please share your experience using this new 16.5 capability.

Jerry “GenPart” Grzenia

What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!

Jerry GenPart — Thu, 19 Apr 2012 17:21:00 GMT

The 16.5 release of Allegro Design Workbench (ADW) provides support for generic models. As you’ve seen in prior releases, ADW supports the typical Cadence SPB front-to-back models – symbols, footprints, etc. Now, we offer generic model support so you can construct new custom models like PSpice, IBIS and other simulation models.

Read on for more details …

We’ll illustrate the highlights of constructing a new model by implementing SI DML model.

In the ADW DBEditor, select File> New> Model Type:

Enter the Model Type Name (SI DML Model), the associated Tool Name (Signoise), the Model Type Abbreviation (DML):

For the Model Dependent of Product Version, select True (you must uprev with each tool release) or False (uprev of data is not required).

Establish the Model Classification per the usual process.

Create the library – identify the Model Type and Logical Library Name:

Establish the Library Flow, for example -

SI DML Model Flow in 16.5:
•   New Model Flow
•   ECO Model Flow

•   Copy As Model
•   Pre release/Release
•   Rules
•   Library Distribution

As always, I look forward to your feedback.

Jerry “GenPart” Grzenia

What's Good About Selection Filters in DEHDL? The Secret's in the 16.5 Release!

Jerry GenPart — Wed, 04 Apr 2012 11:51:00 GMT

In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access -- the Selection Filter helps the user select one or more type of objects in the schematic. This makes it easier to perform operations like aligning objects, distributing them, or moving them to a specific area on the page. The selected objects can also be placed in a group and then group operations can be executed on them.

This provides a more efficient method to quickly, accurately and completely operate on multiple objects – a productivity boost to schematic entry.

Read on for more details …

The Selection Filter is a tool bar which can be docked to any side of the DEHDL window:

In the selection filter, you may select one or more types of objects. After selecting the objects, you can perform operations on them:

When you have selected an object type in the selection filter (for example Symbols):

And draw a selection box over the schematic objects:

Then only those selected objects which have been set in the selection filter (like in the snapshot – Symbols) will be highlighted (and selected):

The following steps provide an example on how to use the selection filter:

1. Draw a selection box and everything gets selected.
2. Set the selection filter to symbols only.
3. Draw a selection box and now only symbols get selected.
4. Select the menu option Group > Create > By Rectangle.
5. Draw a selection box and the symbols in the selection box become part of the group.
6. Select the menu option Group > Add Property…
7. Specify property value pair: FOO = BAR
8. The property gets added to all the symbols which are member of the group.

Please share your experience using this new feature.

Jerry "GenPart" Grzenia

What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New Enhancements!

Jerry GenPart — Tue, 27 Mar 2012 13:51:00 GMT

Address Bus Topology Support

Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is straightforward for a data, bus but becomes more complicated for an address bus. This is illustrated in the diagram below:

In this example there are two strobe nets that control the DATA signals. They are DATA_STROBE0 and DATA_STROBE1 and each connects to two memory SDRAMs. Each bit of the DATA bus connects to a single SDRAM so it's easy to specify which strobe is to be used when simulating any given bit of the DATA bus. For example, when simulating DATA8, DATA_STROBE0 is to be used; when simulating DATA24, DATA_STROBE1 will be used.

The ADDRESS bus is different in that each bit of this bus goes to every SDRAM. This bus is controlled by two clock signals, ADDRESS_CLOCK0 and ADDRESS_CLOCK1. This makes it more complicated to specify which clock is to be used for any given bit of the ADDRESS bus. For example, when simulating ADDRESS0 with SDRAM0 active, ADDRESS_CLOCK0 should be used but when simulating ADDRESS0 with SDRAM3 active, ADDRESS_CLOCK1 should be used.

The 16.3 Bus Setup dialog form allows you to assign strobe or clock nets to each bit of the bus being simulated. This only allows a single strobe or clock to be assigned to any given bit of the bus. Once a bit has been assigned it is no longer available in the Unassigned Bus Xnets list.

To solve this problem this form has been updated in 16.5 to optionally allow multiple bus Xnets to be assigned to the same clock or strobe signal. When a specific clock is selected, the Bus Xnets that have been assigned to another clock will no longer be removed from the Unassigned Bus Xnets list. This allows them to be assigned to multiple clocks/strobes.

Using the example shown above, assume that the ADDRESS bus members are assigned to the ADDRESS_CLOCK nets. In this case you would first select ADDRESS_CLOCK0 and assign all of the ADDRESS nets to that clock. You would then select ADDRESS_CLOCK1 and again assign all of the ADDRESS nets to that clock.

When a bit of the ADDRESS is simulated the software determines which of the two assigned clock nets to use based on the SDRAM that is being activated.

The 16.3 bus analysis report produces all the raw data needed to determine timing closure for a source synchronous interface, but does not perform the needed calculations to arrive at a pass/fail timing test. In 16.5, the timing margin is now included in the bus analysis report.

I look forward to your comments.

Jerry "GenPart" Grzenia

What's Good About APD’s Symbol Editor App Mode? You’ll Need the 16.5 Release to See!

Jerry GenPart — Tue, 20 Mar 2012 17:03:00 GMT

In an IC package design, it is common for the designer to customize the BGA component, or even the die components (if they are still subject to changes by the IC owner) in order to optimize the package substrate for cost and efficiency. In order to do this, changes to the components and physical symbols representing them in the substrate layout are often necessary. Since the 14.2 release, Cadence IC Packaging physical layout tools like APD and Cadence SiP Layout have provided context-based editing commands for making changes to the BGA and die symbols directly within the package substrate design (instead of modifying the library symbols via the symbol (.dra) editor, as would be done for a PCB design).

With the release of 16.5 Allegro Package Designer, these aging BGA and die editor commands are being phased out and replaced with the Symbol Editor application mode. As a package designer, this new application mode environment gives you all the same power of those old commands – and more! – in an intuitive environment specifically geared towards productive editing of your components.

Want to know more details? Read on!

It might be best to watch a video of this feature (available on Cadence Online Support – COS) before reading the exhaustive information below.

IC package designers normally consider the package BGA component as a part of the package design and therefore changeable. In addition, the IC design team may be developing one or more of the dies within the package or SiP concurrently with the package, and thus the package designer may be able to suggest die changes. This means that the package designer may need to be able to add, remove, rename, or move pins and even change the body size of die and BGA components during package layout. As system designs become even more complex and dense, customers are becoming increasingly dependent on system-level floor planning, partitioning and concurrent design. As a result, PCB/Package co-design is developing as a vital requirement for systems customers.

Gone are the large forms that hide areas of your canvas window, the frequent cursor movements between the canvas and the forms themselves, the lack of show element support while editing a symbol, and the inability to run other features and make efficient design trade-offs. Replacing this is a context-sensitive environment where you can move naturally between modifying pins to updating escape routing and bond finger placement; an application mode that reacts to what you are working on, and works to make your life easier. It stays out of the way until it is needed, and fades into the background once you are done with it.

This change may seem like a dramatic design flow impact, but it is really not. The user will still be performing the same edits that they do today, but the manner in which they do them will be much faster and more intuitive. It will also better align with the current use model of the rest of the tool.

The following are some key features of the new 16.5 APD and SiP capabilities.

• You can move seamlessly between editing the symbol and the package substrate. You can move a pin to eliminate a wire-wire DRC at the die side, then move immediately into updating the wire bond pattern to compensate. Or, you could be changing a BGA ball padstack to get more routes through a channel, then go and change the via structure that connects to the ball and update the pin escape.

Here is an example of how a pin was deleted in 16.3:

Here is a screenshot of deleting a pin in 16.5 (using the PCB Editor):

Here is a screenshot of deleting a pin in 16.5 (using the Symbol App mode):

• Full-context editing: You can see the current routing, all the other components in the substrate, etc. all while making edits to the components as necessary. No need to look at separate windows, get in/out of a different command environment, etc. Use show element, highlighting, net coloring, data tips, etc. to get the info you need to make the most intelligent design decisions quickly and efficiently.

Here is an example of a pin being added to the BGA ball pattern in 16.3:

Here is an example of how this is done in 16.5:

• Multi-instance editing. Because the app mode modifies the symbol/component definitions, if you have 4 instances of a die in your design, as an example, adding a pin on one instance through the app mode instantly updates all three other instances with those same changes. The “stretch etch” settings are applied across all instances, as well. So, if each instance of the die had a slightly different fanout pattern, that is compensated for as a pin is moved, deleted, swapped, etc. at each instance level.

• Editing of additional component types. Previously, you could only edit dies and BGAs. Now, if your design flow permits, you can edit any component type by this method -- Modify your plating bar, make changes to that discrete, etc. all from the comfort of that one environment::

• No big, bulky forms taking up screen real estate. The BGA and Die editors had a massive form that you had to use to control everything. Now, all the things you can do in the app mode have been simplified to the point where their settings fit in the options tab of the main window, leaving the full canvas available and visible at all times.

• “Instant on” editing. With the older editors, you had to start the command, pick the component to edit, enter the command, make changes, and then get back out. Depending on the complexity of the component and the level of completeness of the substrate routing, this could take quite some time just to get in/out. Now, there is none of that.

• Context-sensitive RMB menus. This is like all other app modes. There’s no switching between different states or tabs of forms or anything like that. RMB on a pin or set of pins and pick move. The pins show up on your cursor and you can move them around. You can even customize what operations are performed when you do a double-click or a click-and-drag of an object. So, you don’t have to do anything to move a pin beyond dragging it to where you want it to go

I look forward to your feedback on this new 16.5 capability!

Jerry "GenPart" Grzenia