What's Good About Property Changes in DEHDL? The Secret's in the 16.5 Release!
By Gerald "Jerry" Grzenia
on February 7, 2012
In the 16.5 release, all connectivity changes are stored in the hierarchical block directly in Design Entry HDL (DEHDL). Connectivity changes are basically additions or modifications of components, nets, and pin-net connections. The behavior remains the...
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Filed under: Design Entry HDL, ConceptHDL, Constraint Manager, Allegro, Schematic, PCB, Design Entry, Allegro Design Entry, design, SPB16.5, Allegro 16.5, hierarchy, hierarchical schematics, flat schematics, electrical constraints, uprev, property changes
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What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on January 31, 2012
In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application...
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Filed under: PCB Layout and routing, PCB design, Allegro, SI, PCB, PCB SI, layout, PCB Signal integrity, High Speed, Allegro 16.5, signal integrity, 16.5, application mode
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What's Good About APD’s Die Abstract Libraries? You’ll Need the 16.5 Release to See!
By Gerald "Jerry" Grzenia
on January 24, 2012
In System in Package (SiP) 16.3, the co-design die flow introduced the distributed co-design flow concept, where there is no direct interaction with I/O Planner. Die information flowing between Encounter and SiP Layout is done via a die abstract. In flows...
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Filed under: PCB design, Allegro, Librarians, APD, IC Packaging and SiP Design, IC Packaging, PCB, layout, "PCB design", Digital SiP design, Library, design, SPB16.5, Allegro 16.5, PCB design", packaging, die abstract compare, Allegro Package Designer, IC/package co-design, CML, die abstracts
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What's Good About Allegro GRE Constraint Region Support? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on January 18, 2012
The 16.5 Global Route Environment ( GRE ) now allows or prohibits tuning in constraint regions. This functionality was designed to help PCB designers prevent delay routing in constraint regions. This is generally desirable as the space is so tight in...
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Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, "PCB design", GRE, routing, SPB16.5, Allegro 16.5, constraint region
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What's Good About Allegro PCB Router Inset Vias? See for yourself in 16.5!
By Gerald "Jerry" Grzenia
on January 10, 2012
Another high density interconnect (HDI) technology that has gained popularity is inset vias. The 16.5 release has provided new commands added in Allegro PCB Router to support inset vias. Via in Pad pattern has been very popular due to its clear advantage...
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Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, High-Density Interconnect, HDI, Allegro, via, PCB Editor, PCB, layer stacks, layout, "PCB design", design, routing, High Speed, SPB16.5, Allegro 16.5, interconnects, inset vias
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What's Good About Allegro Differential Pair Updates? Look to SPB16.5 and See!
By Gerald "Jerry" Grzenia
on January 4, 2012
The 16.5 Allegro PCB Editor release adds differential pair phase tuning as an alternative to using the mouse guided delay tune command, and also quality improvements for transitions at region boundaries. I’m providing a quick summary this week of...
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Filed under: PCB Layout and routing, PCB design, Differential Pair Support, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, "PCB design", design, differential pairs, SPB16.5, Allegro 16.5
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What’s Good About OrCAD Apps? You Can Try Them for Free!
By Gerald "Jerry" Grzenia
on December 20, 2011
The introduction of Apps in the new Cadence OrCAD Capture Marketplace in the 16.5 release brings a new level of feature customization to the designer in a proven, successful, delivery model. But what does this “design by plug-in” or “app...
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Filed under: Capture CIS, OrCAD Capture, OrCAD, Schematic, Capture-CIS, PCB, Design Entry, Allegro Design Entry, Design Entry CIS, PCB Capture, "PCB design", SPB16.5, Allegro 16.5, OrCAD Capture Marketplace, OrCAD online store, OrCADapps, Team OrCAD, Marketplace, applications
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What's Good About ... ? You'll Need to Open and See!
By Gerald "Jerry" Grzenia
on December 13, 2011
As we approach the Christmas season, many will reflect upon past Christmas times with family, friends, and new acquaintances. As children, we learned about Santa Claus and the fun and excitement of Christmas morning of seeing presents under the Christmas...
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Filed under: PCB design, Christmas
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What's Good About AMS New PSpice Models? They’re in the 16.5 Release!
By Gerald "Jerry" Grzenia
on December 6, 2011
The 16.5 AMS library has a range of new models that can be used in diverse applications such as power supply, regulation and monitoring, and signal isolation. The new models include the following: • MOSFET Drivers • Alkaline Battery • Supervisory...
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Filed under: AMS simulation, Allegro, AMS simulator, AMS, pspice, Library, SPB16.5, Allegro 16.5
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Robert Hanson Tames the Topic of Power on Final Day of Cadence Event
By Team Allegro
on December 2, 2011
On day-three of the Cadence Signal and Power Integrity Three Day Event, the audience was served up a dose of Robert Hanson expertise on managing power delivery networks. Robert covered topics such as developing a bypass system, RLC of a bypass capacitor...
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Filed under: PCB Signal and power integrity, PCB design, PDN, DDR3, IBIS-AMI, Allegro, SI, PCB, PCB Signal integrity, Power Delivery Network, PCI Express, power integrity, PI, Allegro 16.5, OrCAD PCB SI, signal integrity, Robert Hanson
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