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PCB Design Blog

What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6! By Gerald "Jerry" Grzenia on May 20, 2013 Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components... Read More » Comments (1) Filed under: Allegro, Allegro 16.6, Allegro GUI, Allegro PCB Editor, Grzenia, layout, Overlap components by, PCB, PCB design, PCB Editor, PCB Layout and routing, place replicate, placement edit, Quickplace, SPB

What's Good About AMS Data Precision Options? They’re in the 16.6 Release! By Gerald "Jerry" Grzenia on May 13, 2013 Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed... Read More » Comments (0) Filed under: Allegro AMS, AMS, AMS simulation, AMS simulator, Cadence, Cadence Design Systems, design, Grzenia, OrCAD, OrCAD Capture, pspice

What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements! By Gerald "Jerry" Grzenia on May 6, 2013 Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS ( Capture ) product has a few new enhancements for Saving designs. Read on for more details ... Save In the Hierarchy viewer... Read More » Comments (0) Filed under: Allegro, Allegro 16.6, Allegro Design Entry, Cadence Design Systems, Capture, Capture CIS, Capture-CIS, design, Design Entry, Design Entry CIS, Front-end PCB design, Grzenia, SPB

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture By Naveen Konchada on May 2, 2013 Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct... Read More » Comments (0) Filed under: "capture CIS", "PCB design", 16.01, 16.5, 16.6, application note, Appnote, Appnotes, Cadence, Capture, Capture CIS, Capture-CIS, hierarchical schematics, hierarchy, OrCAD, OrCAD Capture, PCB, PCB Capture, PCB design, Schematic

What's Good About ADW’s Design Migration? 16.6 has many new enhancements! By Gerald "Jerry" Grzenia on April 29, 2013 Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables: – Netassembler – Archiver – Purge – Packager It was also less robust with dependencies on external programs, and the... Read More » Comments (0) Filed under: 16.6, ADW, Allegro, Allegro 16.6, Allegro Design Workbench, Cadence, design, design data management, Grzenia, Library

What's Good About FSP’s Design Compare? Check Out 16.6! By Gerald "Jerry" Grzenia on April 18, 2013 The 16.6 Allegro FPGA System Planne r (FSP) product has an extremely helpful Design Compare capability. With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP... Read More » Comments (0) Filed under: 16.6, Allegro, Allegro 16.6, comparing constraints, design, Design Entry HDL, FPGA, FPGA System Planner, FPGA: PCB, FPGA-PCB Co-Design, FPGAs, FSP, Grzenia, layout, PCB, PCB design, PCB Editor, PCB Layout and routing, SPB, Taray

What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release! By Gerald "Jerry" Grzenia on April 16, 2013 The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types: • Schematics (.cpm) • Layout design (.brd, .sip, .mcm... Read More » Comments (0) Filed under: 16.6, Allegro, Allegro 16.6, Allegro Design Entry, constraint databases, constraint difference, Constraint Manager, Constraint-driven PCB Design flow, design, Grzenia, layout, PCB, PCB design, PCB Editor, property, Schematic

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6! By Gerald "Jerry" Grzenia on April 9, 2013 Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer... Read More » Comments (2) Filed under: "PCB design", 16.6, Allegro 16.6, Allegro GUI, Allegro PCB Editor, constraint databases, constraint difference, Constraint Manager, Constraint-driven PCB Design flow, constraints, design, ECSets, electrical constraints, Grzenia, layout, PCB, PCB design, PCB Editor, PCB Layout and routing, SPB

What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements! By Gerald "Jerry" Grzenia on April 3, 2013 The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements: Grouping in Design Entry HDL (DEHDL) Allegro PCB Editor Enhancements Read on for more... Read More » Comments (0) Filed under: 16.6, Allegro 16.6, Allegro PCB Editor, Allegro RF SiP, autoplace, Cadence Design Systems, design, Design Entry, Design Entry HDL, Grzenia, PCB, PCB design, PCB Editor, PCB Layout and routing, placement edit, RF, RF PCB, Schematic, SPB

What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements! By Gerald "Jerry" Grzenia on March 25, 2013 In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models. Read on for more details … Adding Vias Adding a via is easier... Read More » Comments (0) Filed under: "PCB design", "PCB SI", 16.6, Allegro, Allegro 16.6, Allegro PCB SI, Cadence, design, Design Reuse, Grzenia, inset vias, layer stacks, PCB, PCB SI, PCB Signal and power integrity, PCB Signal integrity, SI, SI analysis and modeling, signal integrity, Signal Intregrity, SigXP UI, via

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