Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
By Sathishkumar Balasubramanian
on March 29, 2013
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The...
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Filed under: AMS, AMS Designer, AMS Verification, analog, analog behavioral models, analog/mixed-signal, Cadence, CDNLive, CDNLive 2013, CDNLive SV 2013, EDI, mixed signal, mixed signal methodology guide, Mixed-Signal IP, mixed-signal verification, MS ToT, OpenAccess, SoCs, Tech on Tour, Virtuoso
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"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification
By Sathishkumar Balasubramanian
on February 25, 2013
We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed...
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Filed under: AMS, analog, analog behavioral models, analog/mixed-signal, CDNLive 2013, DVCon 2013, Incisive, Internet of Things, mixed signal, mixed-signal, mixed-signal verification, RNM, Schematic Model Generator, SenseAware, smart devices, SV-DC, Verilog AMS, Verilog-AMS, Virtuoso, Virtuoso environment, wreal
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Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment
By Sathishkumar Balasubramanian
on January 8, 2013
Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for...
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Filed under: AMS Designer, analog, Cadence, CDNLive, Custom, Design Challenges, Digital, Encounter Digital Platform, implementation, mixed signal, mixed-signal, mixed-signal book, mixed-signal methodology guide, Mixed-signal solutions web page, verification, Virtuoso, web page, web site
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Mixed Signal Technology Summit Proceedings Now Available
By Mladen Nizic
on December 13, 2012
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased...
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Filed under: AMS, AMS Verification, analog behavioral models, analog behavoral, analog/mixed-signal, ARM, ARM Cortex M0, ARM-Cortex-M, behavioral models, Cadence, cortex M, Cortex-M0, EDI, Encounter, FTM, functional verification, liberty model, MCUs, microcontrollers, mixed signal, mixed signal design, mixed signal implementation, mixed signal methodology, mixed signal methodology guide, Mixed signal physical implementation, mixed signal physical implementation open access, mixed signal solution, mixed-signal, mixed-signal design, mixed-signal seminars, Mixed-Signal Technology Summit, model validation, oa, OA: OpenAccess, open access, OpenAccess, real number models, real number types, RNM, signal integrity, simulation, Spectre, SPICE, STA, static analysis, static timing analysis, timing model, Verilog-AMS, Virtuoso, wreal
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Mixed-Signal Technology Summit in Japan Provides Technology Updates
By Qi Wang
on November 29, 2012
Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products...
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Filed under: A/MS, AMS, AMS Designer, AMS Verification, AMS-Designer, analog, analog behavioral models, analog on top, analog/mixed-signal, ARM, ARM Cortex M0, ARM-Cortex-M, Cliosoft, Common Power Format, Cortex-M, Cortex-M0, Encounter, IC 6.1, LDE, Matlab, metric-driven verification, microcontrollers, micro-controllers, mixed signal, mixed signal design, mixed signal methodology, mixed-signal, mixed-signal book, Mixed-Signal On Top, Mixed-Signal Technology Summit, MS ToT, oa, open access, OpenAccess, real number, Tech on Tour, TowerJazz, UVM, Verilog-AMS, Virtuoso, Virtuoso-AMS, wreal
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Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes
By Andreas Lenz
on November 15, 2012
Are you working in the area of mixed signal? Then you may want to exchange information and experiences with other engineers. At the Cadence Community, a new Mixed-Signal Design Forum has been launched, providing a place to discuss topics that cross between...
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Filed under: analog on top, Andreas Lenz, Cadence Community, CPF, Encounter, forum, ITDB, mixed signal, mixed-signal, mixed-signal forum, mixed-signal training, OpenAccess, Virtuoso
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Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums
By Sathishkumar Balasubramanian
on November 14, 2012
The recently concluded ARM TechCon 2012 , the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's...
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Filed under: 14nm, 20nm, AMS Designer, ARM, ARM Cortex M0, ARM Techcon, ARM Technology Symposium, ARM-Cortex-M, ChipEstimate, Cortex-M0, EDI, mixed signal, mixed-signal, mixed-signal book, mixed-signal design, Virtuoso
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Recent Events Show That Customer Interest in Mixed-Signal Remains High
By Qi Wang
on October 30, 2012
The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based...
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Filed under: AMS Verification, analog/mixed-signal, ARM, ARM Cortex M0, ARM Techcon, cortex M, Cortex-M, Cortex-M0, mixed signal, mixed signal design, mixed signal methodology, mixed signal methodology guide, mixed signal solution, mixed-signal, mixed-signal book, mixed-signal design, mixed-signal methodology, Mixed-Signal Methodology Book, Mixed-Signal Tech Summit, Mixed-Signal Technology Summit, mixed-signal ToT, MS ToT, OA: OpenAccess, open access, OpenAccess, Tech on Tour, Technology on Tour, tech-on-tour
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Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership
By Sathishkumar Balasubramanian
on October 19, 2012
A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso...
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Filed under: AMS, AMS Designer, ARM, ARM Cortex M0, Cadence, EDI, Encounter Power System, Encounter Timing System, EPS, ETS, IUS, microcontrollers, mixed signal, mixed signal methodology guide, mixed-signal, Mixed-Signal On Top, MS ToT, PVS, TSMC, UVM, Virtuoso
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ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution
By Sathishkumar Balasubramanian
on September 25, 2012
I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of Smaller Chips," that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM...
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Filed under: ARM, Balasubramanian, Cortex-M, Cortex-M0, DAC, demo, fuel injection system, Incyte, MCUs, microcontrollers, micro-controllers, System Design Kit, Virtuoso
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