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Silicon Signoff and Verification Blog

Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through http://support.cadence.com...  Read More »
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Voltus – Massive Parallelism Speeds Power Integrity Analysis and Signoff Closure

Performance, capacity, accuracy. These are the three criteria that IC design teams want most in a power analysis solution. By using a massively distributed, parallel compute engine along with a hierarchical capability, the Cadence Voltus IC Power Integrity...  Read More »
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Tackling Complexity at the System-to-Silicon Verification Summit

System-to-silicon verification is the biggest challenge our industry faces today. It's also the biggest opportunity for both design teams and EDA vendors. Consider the productivity and time-to-market improvements that we could yield in the coming...  Read More »
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Interview with Lip-Bu Tan, Part 1 – How Cadence is Positioned to Build Upon Success

Under the leadership of Lip-Bu Tan , Cadence President and CEO, Cadence has experienced strong growth during the past four years. In addition to steadily growing its revenue and hiring hundreds of new R&D engineers, Cadence has enhanced its product...  Read More »
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DAC 2013 Panel: Where’s the Innovation in Timing Signoff?

Has there been enough innovation in timing signoff? Probably not, given the enormous amount of time that timing signoff and closure can take, especially at advanced nodes where there can be hundreds of multi-mode, multi-corner (MMMC) timing views. At...  Read More »
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Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff...  Read More »
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis

Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure...  Read More »
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CDNLive Silicon Valley 2013 Proceedings Available for Download!

CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations...  Read More »
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Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current...  Read More »
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