New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
By Adam Sherer
on May 7, 2013
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE...
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Filed under: low-power, power, low power, PSO, UPF, CPF, IES, verification, CPF 2.0, power shutoff, low-power design, IEEE 1801, IEEE 1801-2009, DPA, UVM, CDNLive, Incisive, Adam Sherer, Incisive Enterprise Simulator
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Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
By Pete Hardee
on February 12, 2013
I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for...
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Filed under: low-power, low power, low-power design, ARM, mixed-signal low-power, ultra low power, microcontrollers, internet of things, benchmarks, ULP, low power benchmarks, EEMBC, benchmarking
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New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification
By Sumeet Aggarwal
on December 10, 2012
All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for...
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Filed under: low power, mixed-signal, mixed signal, Conformal Low Power, Digital Front-End Design, CPF Macro Modelling, Power Intent Export Assistant, design CPF, Mixed Signal Verification, CLP, Virtuoso Schematic Editor, VSE, Virtuoso, PIEA, mixed-signal low-power, Cadence Online Support, COS, Conformal
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Low-Power Technology Summit Proceedings Now Available
By Pete Hardee
on December 5, 2012
On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view...
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Filed under: Hardee, PSO, shutoff, MSV, DVFS, Dynamic power, mixed-signal, mixed signal, MVt, power shutoff, power gating, power shut-off, low-power design, Luke Lang, Qi Wang, Substrate bias, body bias, reverse bias, freescale, kinetis, multi-bit flops, power optimization, back bias, ground level shifter, Low Power Mixed Signal Verification, Anis Jarrar, POP, ARM, Broadcom, physical IP, low power summit, Jan Rabaey, Berkeley Wireless Research Center, BWRC, power domains
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Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
By Pete Hardee
on November 29, 2012
The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First...
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Filed under: Hardee, PSO, MSV, DVFS, MVt, Encounter, low-power design, Advanced Features, low power summit, power domains, voltage domains, low power survey, supply voltages
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Packed House Expected for Cadence Low-Power Technology Summit
By Pete Hardee
on October 16, 2012
It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full...
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Filed under: low-power, mixed-signal, mixed signal, freescale, POP, ARM, Broadcom, physical IP, low power summit, Jan Rabaey, Berkeley Wireless Research Center, BWRC
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Your First Low-power Verification Project - Webinar
By Adam Sherer
on October 11, 2012
So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls...
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Filed under: low-power, PSO, UPF, CPF, IES, power shutoff, IEEE 1801, Functional Verification, webinar
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Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
By Pete Hardee
on September 17, 2012
CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012...
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Filed under: low-power, low power, MSV, CPF, power analysis, Palladium, MVt, Common Power Format, Encounter, power shut-off, 28nm, low-power design, Sorin Dobre, Qualcomm, advanced verification, CDNLive, CDNLive!, freescale, kinetis, CDN Live, Conformal Low Power, Low Power Mixed Signal Verification, CPF Macro Modelling, Anis Jarrar
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RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling
By Sumeet Aggarwal
on August 10, 2012
Why do you define macro models? Luke Lang , Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black...
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Filed under: low power, CPF, low-power design, Rapid Adoption Kits, Conformal Low Power, Functional Verification, Formal Verification, Common Power Format 1.0, Low Power Mixed Signal Verification, Advanced Features, Digital Front-End Design, CPF Macro Modelling, RAK, Hierarchical Integration, Power Intent Comparison, online support, Cadence support, RAKs, macro models
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Mixed Signals from European Low-Power Designers
By Pete Hardee
on July 25, 2012
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it...
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Filed under: low-power, low power, MSV, DVFS, Dynamic power, wreal, mixed-signal, mixed signal, Common Power Format, power shutoff, power gating, reliability, Moore's Law, Europe, European designers
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