Does Substrate Biasing Have a Future?
By Pete Hardee
on February 6, 2012
At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive...
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Filed under: low-power, PSO, library, power gating, Encounter, power shut-off, low-power design, Substrate bias, body bias, reverse bias, biasing
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What’s Next in Low Power?
By Qi Wang
on January 24, 2012
Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate...
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Filed under: power, low power, UPF, CPF, GUC, advanced verification, UVM, tapeouts
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Low Power Design in 2011 and Predictions for 2012
By Pete Hardee
on December 22, 2011
It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward...
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Filed under: low-power, Hardee, low power, CPF, power analysis, Palladium, low-power design, FinFETs, Moore's Law', 2012 predictions, ESL, energy harvesting, DPA
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Low Power Marketing Hype – And What They Don’t Tell You
By Pete Hardee
on November 30, 2011
Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm...
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Filed under: green, thermal, low-power, low power, system power, low-power design, Thanksgiving, SmartPower, LCD, low temperature, HDTV, LED, Black Friday, reliability
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Si2 Interoperability Guide V2.0 Available for Download
By Qi Wang
on October 31, 2011
Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format...
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Filed under: low-power, power, low power, UPF, CPF, CPF 2.0, Common Power Format, Si2, OpenLPM, low-power design, IEEE 1801, IEEE 1801-2009, tutorial, interoperability guide
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Cadence Low Power Guru Wins Si2’s Distinguished Service Award
By Pete Hardee
on October 21, 2011
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Filed under: low-power, low power, UPF, CPF, CPF 2.0, Common Power Format, LPC, Si2, OpenLPM, low-power design, IEEE 1801, Qi Wang
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Another Expert’s View on Power Intent and Hierarchy
By Pete Hardee
on September 21, 2011
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Filed under: low-power, power, low power, UPF, IP, CPF, Common Power Format, Si2, low-power design, IEEE 1801, Open Low Power Methodology, Luke Lang
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Low-power Keeps Gate-Level Simulation Forever Young
By Adam Sherer
on September 8, 2011
Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement...
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Filed under: low power, UPF, CPF, simulation, IES, verification, low-power design, IEEE 1801, shutdown, gate simulation, Ann Mutschler, gate-level simulation
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An Expert’s View on Power Formats and Methodology
By Pete Hardee
on August 24, 2011
In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress...
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Filed under: low-power, low power, UPF, CPF, Silicon Integration Initiative, Common Power Format, Si2, OpenLPM, low-power design, IEEE 1801, Sorin Dobre, Qualcomm
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Low Power Design -- Alive and Well at DAC
By Pete Hardee
on June 14, 2011
Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing...
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Filed under: low-power, low power, UPF, CPF, Palladium, Silicon Integration Initiative, Common Power Format, Si2, DAC, OpenLPM, low-power design, IEEE 1801
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