Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
By Stella Murphy
on August 3, 2011
Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post . What is SR...
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Filed under: Design IP, controller IP, IP, PCI Express 3.0, Gen3, video, PCI Express, PCIe, SR-IOV, PCIe Gen3
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Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)
By Stella Murphy
on July 28, 2011
This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering...
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Filed under: Design IP, IP, Gen3, PCI, PCI-SIG, PIPE, video, SAS RAID, PCI Express, PCI Express Gen3, PCIe
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Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon
By Stella Murphy
on June 30, 2011
At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's...
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Filed under: Design IP, controller IP, PCI Express 3.0, Gen3, PCI, PCI-SIG, PIPE
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Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes”
By Marc Greenberg
on April 20, 2011
A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with ECC and my system has the capability to use write data masks and partial-word writes. DDR3 has a reset pin, why can't I just reset it? Why do I need to initialize...
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Filed under: memory, DDR, Denali, controller IP, IP, SoC, DRAM, security, MMAV, encryption, memory IP, VIP, Princeton, reboot
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New Memory Technologies, New Possibilities
By Neil Hand
on April 11, 2011
As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory...
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Filed under: Wide-IO, DDR4, memory, DDR, Design IP, storage, SoC Realization, Denali, controller IP, IP, SoC, wide I/O
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The 3D SSD
By Steve Leibson
on November 29, 2010
You need three things from a solid-state disk (SSD): speed, capacity, and reliability. You need three things from a portable SSD: speed, capacity, reliability, and diminutive size. And you can’t get much smaller than packing an SSD into the form factor...
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STT-MRAM -- from Seagate???
By Steve Leibson
on November 5, 2010
On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car, and drove from Minneapolis to Bloomington to attend a special disk drive conference being held by the leading vendor of cutting-edge 5.25-inch hard disk drives--Imprimis...
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Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option
By Steve Leibson
on October 21, 2010
Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only...
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Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbytes
By Steve Leibson
on October 19, 2010
Stop me if you’ve heard this one. The fastest way to get high performance from an SSD is to bypass the disk interface and plug the SSD directly into the PC’s PCIe port. Vendors of high-performance (read “expensive”) SSDs do just that. So just where does...
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Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port
By Steve Leibson
on October 18, 2010
Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier this year ( How does a hybrid SSD/optical drive make sense? ) by integrating the SSD with the optical drive controller and making both the optical and solid-state drives...
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