Home > Community > Blogs > Design IP
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence IP blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Design IP Blog

Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance

It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly...  Read More »
Comments (0)
Filed under: , , , , , , , , , , , ,
Martin Lund on the Future of IP (Video Interview)

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually...  Read More »
Comments (0)
Filed under: , , , , , , ,
Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post . What is SR...  Read More »
Comments (0)
Filed under: , , , , , , , , ,
Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering...  Read More »
Comments (0)
Filed under: , , , , , , , , , ,
Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's...  Read More »
Comments (0)
Filed under: , , , , , ,
Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes”

A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with ECC and my system has the capability to use write data masks and partial-word writes. DDR3 has a reset pin, why can't I just reset it? Why do I need to initialize...  Read More »
Comments (0)
Filed under: , , , , , , , , , , , , ,
New Memory Technologies, New Possibilities

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory...  Read More »
Comments (0)
Filed under: , , , , , , , , , , ,
The 3D SSD

You need three things from a solid-state disk (SSD): speed, capacity, and reliability. You need three things from a portable SSD: speed, capacity, reliability, and diminutive size. And you can’t get much smaller than packing an SSD into the form factor...  Read More »
Comments (0)
STT-MRAM -- from Seagate???

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car, and drove from Minneapolis to Bloomington to attend a special disk drive conference being held by the leading vendor of cutting-edge 5.25-inch hard disk drives--Imprimis...  Read More »
Comments (0)
Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only...  Read More »
Comments (0)
View older posts »
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.