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Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

Comments(0)Filed under: Industry Insights, chip estimate, Incyte, SoC, Analog, IP, Mixed-Signal, mixed signal, subsystems, IP quality, system on chip, ChipEstimate.com, Traidman, chip estimation, chip planning, design IP, Adam Traidman, silicon IP

As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today he manages the Cadence chip planning business unit, and his responsibilities include ChipEstimate.com, which has become a leading industry portal and information resource for design and verification IP.

In this interview Traidman talks about trends in the third-party IP business, IP subsystems, IP quality, chip planning, advanced nodes, mixed-signal integration, and what you'll find at ChipEstimate.com.

Q: Adam, you had a significant involvement in the IP market as CEO of Chip Estimate. What led up to that?

A: I started my career working in computer software at the NASA Jet Propulsion Laboratory, working on deep space exploration technologies. Later, I returned to my original career plan, semiconductor design, and worked in the ASIC division of Texas Instruments. I then moved on to Monterey Design Systems [former EDA company], an exciting startup at the time, where I was working as an AE for physical design.

I then went to a small company later acquired by Adaptec, and this is where I began to get broader experience with a wide variety of semiconductor design IP from foundation IP to microprocessors.  After years of physical design and verification, one day I got a call from a former colleague from Monterey who had founded a company called Hier Design. They were working on floorplanning tools for FPGAs and were funded by Xilinx and Cadence. In an interesting career twist, I joined them in a technical sales capacity.  We were acquired by Xilinx less than a year later.

In 2004, I was asked to come and work at Giga Scale Integration Corp., which we later renamed to Chip Estimate. I was thinking that my title might be business development, but the board had other plans and asked me to become president and CEO immediately. I accepted that responsibility and at that point got a lot more involved in the semiconductor IP market, since IP was such an important component in the value proposition of our tool. I became active in the VSIA [Virtual Socket Interface Alliance, no longer in existence] and the FSA [Fabless Semiconductor Association, now Global Semiconductor Alliance] and a number of other industry trade organizations.  In March of 2008, Chip Estimate was acquired by Cadence.

Q: What's your role at Cadence today?

A: Today I have the pleasure of leading our Chip Planning Solutions business unit. We are a semi-autonomous organization within Cadence, which helps us maintain the neutrality of the ChipEstimate.com portal and brand.

Q: What do you see as the most important trends in the IP market today?

A: We're seeing continued and accelerating consolidation of the IP market. The larger players are growing both horizontally and vertically so they can provide deeper, more integrated solutions. Here at Cadence we made a very aggressive move with Denali and we are doing a great job in the memory area. We are expanding to interesting protocol IP that our customers value, like PCI Express, and I feel we'll continue to grow horizontally over time. By growing vertically I mean providing full analog and digital solutions, drivers, and verification IP, and I think we're doing a great job at that.

Another trend is that large semiconductor companies who would previously rarely consider purchasing external IP - except for perhaps an ARM core - are now changing their strategy and are beginning to embrace external IP. A key enabler is the protocol IP space, where there is really no point in investing internally and creating a piece of IP that is designed to meet a spec. You can often buy it off the shelf a lot more quickly and verify its quality.

Q: Is there a trend towards IP subsystems? And what is an "IP subsystem," anyway?

A: In my mind an IP subsystem is a set of smaller components that together represent a higher level of value. There is a trend towards subsystems because, as the industry matures, designers will find value in larger building blocks. Our building blocks have evolved up through several levels of abstraction. Instead of customers coming to us and asking for the individual PLLs and DLLs and I/Os, they now come to us and say "we'd like a completely verified digital and analog DDR4 solution that's pre-tested and perhaps even laid out in a specific process technology."

Q: In the past there have been complaints about IP quality. Is the industry making any progress?

A: I think that the quality of IP has definitely gone up, because the companies producing it have matured, and they have honed their design and engineering processes and learned from the past.

However, attempts to attach industry standard quality metrics have not yet had a big impact. A lot of great tools and metrics were created, but there were practicalities of business and confidentiality that effectively kept the industry from embracing those quality metrics. They're still out there and it would be great to see them embraced.

IP quality measurements have been very effective in individual cases. An example is TSMC with its IP9000 program. They worked with their ecosystem providers and came up with very strict quality standards, which they can police and monitor because they own the fab.

Q: What percentage of chips does reusable IP consume today, compared to new custom logic?

A: We actually have some hard data on that from the ChipEstimate.com database, where we collect aggregate, non user-specific information on chip estimations. We have stats on what percentage of a die is new logic versus IP. We've seen the IP portion grow from around 40% in 2004 to 70% to 80% today in ASICs and ASSPs. We have well over 100,000 chip estimations, so our data is quite extensive.

I believe that the secret sauce that is added to most modern chips in terms of brand-new logic is actually quite small - a quarter of the chip or less. I would even say that in many cases, people are adding more value in software than they are in hardware.

Q: Are you seeing an increasing amount of analog IP?

A: Definitely. Nearly any SoC is a mixed-signal chip today. A modern SoC has physical interfaces that require SerDes, and most I/Os are by nature analog anyway. This doesn't mean a given company needs to have expert analog designers, because they can buy that analog expertise through IP. But it does mean that there's analog everywhere.

Q: What is the role of chip planning, and what does Cadence offer?

A: Chip planning tools help users perform architectural exploration and make tradeoffs in power, performance, area, and cost. They help with the IP selection phase. You can quantify the economic impact of an engineering decision or an IP decision and optimize your design specs very early.

Cadence has two chip planning products. The first is Cadence InCyte Chip Estimator, which is offered in a free starter version and a licensed product. The licensed product is more accurate and it provides foundation IP, foundry and process-specific estimates. The second product is the Cadence Chip Planning System, which is the enterprise version. It looks very similar to InCyte but it can be customized with internal IP models, foundation IP models, and manufacturing and process technology models to provide customized and highly tuned estimation.

Q: What's happening at the ChipEstimate.com portal these days?

A: The core value of ChipEstimate.com is the large database of design and verification IP, comprised of nearly 10,000 components from around 250 IP suppliers and foundries. Once you've looked through the database you can import that IP into a free or licensed copy of the Cadence InCyte Chip Estimator, where you can obtain technical or economic metrics about the chip you're building.

The portal is growing quite well. With ChipEstimate.TV, we produce video content that helps ChipEstimate.com users make better decisions about which IP to include in their next design. We have the IP Insider blog by John Blyler, and we publish a bi-weekly newsletter called IP Connections. Meanwhile the user community has continued to grow aggressively. I continue to be amazed at how many people are coming to learn about the IP industry through ChipEstimate.com.

Richard Goering

 

 

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