The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book authored primarily by Cadence R&D experts, titled Advanced Verification Topics, shows how to use metric-driven verification (MDV) and UVM with mixed-signal and low-power designs as well as multi-language verification environments and acceleration.
In 2010 Cadence published A Practical Guide to Adopting the Universal Verification Methodology (UVM), a comprehensive guidebook to UVM. So why write an "advanced topics" book now? Adam Sherer, product marketing director at Cadence and author of the new book's preface, told me that "as we dive below 40nm and into advanced nodes, it's not just a digital world any more. Customers have mixed-signal in there, they need to move up to TLM to handle complexity, and they need MDV." Further, as he pointedly noted, customers need to do some advanced power management at advanced nodes or the silicon will melt.
"The book is for advanced verification engineers and engineering managers who are trying to decide what to tackle next, and want to know how they can improve their productivity by taking a step beyond UVM," Sherer said. He noted that the new book assumes some knowledge of UVM, and if readers don't have that, A Practical Guide to Adopting the Universal Verification Methodology is a great place to start.
The new book discusses extensions to UVM, or "specializations," that are not yet part of the Accellera Systems Initiative standard. As the preface notes, UVM provides a "foundation for specialization," such as extensions needed to support acceleration. But it also notes that specializations built on standards must use open source code and open documentation. That's been done with Advanced Verification Topics.
Metric-Driven Verification and UVM
The first chapter of the book provides a basic overview of MDV, which uses verification planning and coverage metrics to evaluate and guide the verification process. It's a natural complement to UVM, Sherer noted. While UVM helps engineers build reusable tests and test sequences, it can't assess the value of the tests with respect to the verification plan and verification closure. That's where MDV comes in. It helps ensure adequate coverage, measures progress against the verification plan, and ultimately provides meaningful answers to the biggest of all verification questions, "am I done yet?" Other chapters in Advanced Verification Topics are as follows:
UVM and Metric-Driven Verification for Mixed-Signal. This chapter explains why MDV should be used for analog, discusses analog verification planning, and shows how to construct a UVM-MS (UVM-Mixed Signal) verification environment. It describes coverage, assertions, analog model creation, and using UVM-MS verification blocks.
Low Power Verification with the UVM. This chapter presents low-power verification challenges, describes power-aware verification planning, and shows how to configure a power-aware UVM environment.
Multi-Language UVM. This chapter shows how to create UVM Verification Components, called UVCs, that work in environments with more than one language. It provides details about the use of UVM SystemVerilog with the e language and SystemC.
Developing Acceleratable UVCs. Standard UVCs are not architected for acceleration. This chapter presents an approach to UVCs that reuses the stimulus defined in the UVM simulation environment, communicates using the Accellera Systems Initiative SCE-MI standard, and supplies data for MDV.
Advanced Verification Topics is co-authored by Bishnupriya Bhattacharya, John Decker, Gary Hall, Nick Heaton, Yaron Kashai, Neyaz Khan, Zeev Kirshenbaum, and Efrat Shneydor. All work for Cadence except Neyaz Khan, senior scientist at Maxim Integrated Products. The book is available from Amazon. Further information and a preview are available at the Cadence web site.