In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July. At the recent ARM TechCon conference, attendees heard the story of this development and its challenges in a paper presented by ARM, Cadence and Samsung engineers.
The paper was titled "20nm Logic Test Chip Implementation by Samsung, ARM and Cadence." It was presented by Taejoong Song, principal engineer at Samsung; Imran Iqbal, principal design engineer at ARM; and Bimal Gisuthan, senior applications engineer at Cadence. Proceedings are available to conference attendees at the ARM TechCon web site.
Samsung provided the 20nm high-k metal gate (HKMG) process that was used for the test chip, and Song began the presentation with an overview of the process and its development. Noting that the 20nm process provides both low power and high performance, he noted that it's 15% faster than the Samsung 28LPH process and 35% faster than the Samsung 28LP process. However, there were some process challenges, including short-channel effect, complicated device structures, and self-aligned vias.
The process also posed some design challenges, including aggressive design rules, parasitic variation in process corners, and "harsh" electro-migration. A "pre-emptive" approach to placement and routing was needed, and part of the collaborative effort went into "routing enablement" for 20nm. This enablement included router support for a mix of bidirectional and uni-directional routing, metal pitch rules for preferred and non-preferred directions, and via rules for 20nm.
Stepping Up to nSTEP
Iqbal spoke about nSTEP microcontroller implementation using the Cadence 20nm Silicon Realization flow. He talked about the goals of the three-way collaboration, which were as follows:
- Enable a simple ARM core for early 20nm technology demonstrator
- Investigate place and route issues
- Understand standard cell design trade-offs
- Verify functionality of the 20nm process
He also talked about the nSTEP reference system (STEP = System Test Evaluation Platform), nothing that it includes the Cortex-M0 32-bit CPU, two banks of SRAM, and external bus interfaces. It's a good test platform because all it needs are basic standard cells. The 20nm test chip project actually used two variants of nSTEP. The HP (high performance) version used 12-track standard cells and targeted 200MHz, while the HD (high density) version used more aggressive 9-track cells and targeted 100MHz.
Iqbal went into some detail about the floorplan, which was pad-limited with special corner pad spacing. He identified several challenges, including spacing of corner pads, placement of memory macros and endcap cells, and density requirements that called for special filler cells. He also noted that setup time was fairly easy to meet, but designers ended up fixing hold violations at four different corners.
Silicon Realization Flow
Gisuthan provided more information about the design tools used in the test chip effort. He cited the use of the Cadence Encounter RTL Compiler, Incisive Enteprise Simulator, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, and Encounter Test. The design flow looked like this:
"It's the same flow used at 40nm and 32nm, but the difference is that every step of the flow was 20nm aware," Gisuthan said. This includes placement, routing, and clock tree synthesis. One "unique challenge" was power planning. He showed how an aggressive, differential IR drop requirement (25 millivolts) led to a very dense power structure with a power plan that encompassed metal layers 3 through 9. He also described the team's challenges in fixing hold violations with a 150ps margin, and noted that some special delay cells were needed.
Gisuthan also provided an in-depth view of the "routing enablement" for 20nm that Song had noted earlier. "Given so many changes in design rules, it's important for a router to be 20nm ready and to achieve fast automated DRC coverage," he said. "In this respective NanoRoute performed very well." He discussed a couple of rules that caused challenges, including a cluster via rule and a non-preferred direction spacing rule.
"In a short time we were able to achieve two unique implementations of the nSTEP microcontroller," Gisuthan concluded. "We validated the Cadence 20nm digital methodology including Encounter Digital Implementation System implementation and signoff, and tested and validated Samsung libraries. Very strong collaboration between Cadence, ARM and Samsung was a key component of this 20nm success."
Other blog posts about ARM TechCon 2011 papers:
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs
ARM TechCon Paper: Why DRAM Latency is Getting Worse
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
ARM TechCon Paper: Early Architectural Planning with a Digital Implementation Flow