12 Hot EDA Topics – 78 DAC Demo Sessions
By Richard Goering
on May 24, 2012
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running...
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Filed under: Industry Insights, ARM, DAC, low power, Analog, verification, IP, Mixed-Signal, mixed signal, ECO, VIP, custom, system level, 20nm, 3D IC, 3D-IC, signoff, DAC 2012, product demos, DAC demo suites, demo suites, Cadence demos
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DAC 2012: “IP Talks!” Reveals Latest in Semiconductor IP
By Richard Goering
on May 24, 2012
If you want to know what's new in the world of semiconductor intellectual property (IP), the place to be is at the IP Talks! presentations at the Cadence ChipEstimate.com booth at the Design Automation Conference ( DAC 2012 ) June 4-6. Over this three...
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Filed under: Industry Insights, ARM, DAC, SoC, IP, ChipEstimate, Cadence, system on chip, John Heinlein, IP Talks!, semiconductor IP, DAC2012, IP Talks
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User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)
By Richard Goering
on May 23, 2012
Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims...
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Filed under: Industry Insights, ARM, Encounter, broadcom, CDNLive!, IR drop, useful skew, CTS, ccopt, clock concurrent optimization, clocking, Azuro, Cortex-A9, CDN Live, timing skew, Lampaert, clock tres synthesis, Koen Lampaert, timing windows
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Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
By Richard Goering
on May 21, 2012
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries...
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Filed under: Industry Insights, Si2, SiP, Standards, stacked die, 3D, TSV, GSA, 3D IC, 3D-IC, wide i/o, foundry, Potts, 2.5D, wide io, GSA 3D IC, via, OSAT, thernal, power density, Ken Potts
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Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
By Richard Goering
on May 17, 2012
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new...
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Filed under: Industry Insights, 3D ICs, SoC, Semico, IP, Kapoor, IP quality, system on chip, PCI Express, semiconductor IP, PCIe, silicon IP, 3D-ICs, NVM Express, NVMe, IP subsystems, system-driven IP, Impact, Feldhan, IP ecosystem, design factory
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How IP Subsystem Will Speed NVM Express (NVMe) Adoption
By Richard Goering
on May 15, 2012
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together...
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Filed under: Industry Insights, VIP, memory, storage, SoC Integration, PCI Express, NAND flash, PCIe, firmware, SSDs, NVM Express, SATA, NVMe, verificationi IP, solid state drives, IP subsystem, non-volatile memory, NVMe controller
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In-Circuit Acceleration – A New IC Verification Use Model
By Richard Goering
on May 15, 2012
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification...
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Filed under: Industry Insights, Palladium, SystemC, virtual platforms, verification, Incisive, Verification IP, VIP, acceleration, emulator, multi-core, debugging, ICE, in-circuit emulation, System Development Suite, FPGA prototyping, Virtual System Platform, Verification Computing Platform, Palladium XP, RTL simulation, IC verification, software deveopment, AVIP, development platform, rapid prototoyping, in-circuit acceleration, accelerated VIP, virtuaul prototypes, simulation acceleration
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Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
By Richard Goering
on May 14, 2012
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49...
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Filed under: Industry Insights, Palladium, DAC, ESL, Verification IP, VIP, emulation, embedded software, co-development, hardware/software, 28nm, system level, yield, 20nm, System Development Suite, FPGA prototyping, Design Automation Conference, LSI, 14nm, Cadence at DAC, IBM: Samsung, HW/SW co-design, DAC breakfasts
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Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
By Richard Goering
on May 14, 2012
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability...
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Filed under: Industry Insights, ARM, DAC, low power, Analog, Mixed-Signal, mixed signal, NXP, ST, variability, custom/analog, Design Automation Conference, layout dependent effects, LDE, Cortex-M0, Cadence at DAC, DAC lunches, MCU
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Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test
By Richard Goering
on May 10, 2012
Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction...
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Filed under: Industry Insights, Encounter, RTL Compiler, DFT, ATPG, test, ATE, Encounter Test, MBIST, Logic BIST, memory BIST, scan, JTAG, LBIST, automotive electronics, in-system testing, MISR, built-in self test
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