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Industry Insights Blog

Electromigration – What IC Designers Need to Know

If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in...  Read More »
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IBM Lithography Expert: Making 10nm IC Design Possible

Development work is underway on the 10nm process node - but can we get there with conventional lithography? In a recorded presentation available at the Cadence web site, Lars Liebmann, distinguished engineer at IBM, says yes - but he notes that it will...  Read More »
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3D-IC Working Group—Tool Support Needed, But “Gaps” May Be Narrowing

Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and methodologies, according to presenters at a recent meeting...  Read More »
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Designer View – RTL Synthesis Success Strategies at 28nm and Below

RTL synthesis is not a simple pushbutton tool, especially at 28nm and below. In a recorded presentation at the Cadence web site Ramesh Rajagopalan, chip lead for physical implementation of networking SoCs at Cisco Systems, shares some of his company's...  Read More »
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Q&A: Kathryn Kranen Discusses Jasper, Formal Verification, and the Cadence Acquisition

Few individuals have been as visible and influential in the EDA industry as Kathryn Kranen, CEO of formal verification pioneer Jasper Design Automation until its acquisition by Cadence in June 2014. Kranen was also CEO of Verisity Design in the late 1990s...  Read More »
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Flash Memory Summit: 3D NAND Flash Faces Cost, Reliability Challenges

3D NAND Flash architectures will provide the best option for increasing storage densities in future years, according to panelists at a plenary session at the Flash Memory Summit Aug. 5, 2014. But given the large manufacturing investment required, and...  Read More »
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Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Power signoff isn't just about digital logic—analog and custom digital blocks in SoCs need power integrity analysis as well. That's why Cadence today (Aug. 4, 2014) is introducing the Voltus-Fi Custom Power Integrity Solution, which provides...  Read More »
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Designer View – How Emulation/Virtual Prototyping “Hybrid” Speeds Software Development

200X. That's the number with which Moshe Berkovich, senior engineer at fabless semiconductor provider CSR , started a 15-minute talk that is now a recorded presentation on Cadence.com. And 200X is the performance improvement that his team was able...  Read More »
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Archived Webinar – An Introduction to High-Level Synthesis (HLS)

High-level synthesis (HLS) is rapidly entering the IC design mainstream - but how much do you know about this emerging technology? A recently archived Cadence webinar sets the record straight about what HLS is (and is not), how it works, who's using...  Read More »
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Designer View – Getting the Best Use From Static Low-Power Verification

Do you want assurance that your system-on-chip (SoC) netlists are "power clean?" In a recorded presentation on the Cadence web site, Harshat Pant, principal engineer at Broadcom, shows how static low-power verification can provide that assurance...  Read More »
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