In-Circuit Acceleration – A New IC Verification Use Model
By Richard Goering
on May 15, 2012
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification...
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Filed under: Industry Insights, Palladium, SystemC, virtual platforms, verification, Incisive, Verification IP, VIP, acceleration, emulator, multi-core, debugging, ICE, in-circuit emulation, System Development Suite, FPGA prototyping, Virtual System Platform, Verification Computing Platform, Palladium XP, RTL simulation, IC verification, software deveopment, AVIP, development platform, rapid prototoyping, in-circuit acceleration, accelerated VIP, virtuaul prototypes, simulation acceleration
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How IP Subsystem Will Speed NVM Express (NVMe) Adoption
By Richard Goering
on May 15, 2012
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together...
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Filed under: Industry Insights, VIP, memory, storage, SoC Integration, PCI Express, NAND flash, PCIe, firmware, SSDs, NVM Express, SATA, NVMe, verificationi IP, solid state drives, IP subsystem, non-volatile memory, NVMe controller
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Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
By Richard Goering
on May 14, 2012
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49...
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Filed under: Industry Insights, Palladium, DAC, ESL, Verification IP, VIP, emulation, embedded software, co-development, hardware/software, 28nm, system level, yield, 20nm, System Development Suite, FPGA prototyping, Design Automation Conference, LSI, 14nm, Cadence at DAC, IBM: Samsung, HW/SW co-design, DAC breakfasts
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Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
By Richard Goering
on May 14, 2012
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability...
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Filed under: Industry Insights, ARM, DAC, low power, Analog, Mixed-Signal, mixed signal, NXP, ST, variability, custom/analog, Design Automation Conference, layout dependent effects, LDE, Cortex-M0, Cadence at DAC, DAC lunches, MCU
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Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test
By Richard Goering
on May 10, 2012
Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction...
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Filed under: Industry Insights, Encounter, RTL Compiler, DFT, ATPG, test, ATE, Encounter Test, MBIST, Logic BIST, memory BIST, scan, JTAG, LBIST, automotive electronics, in-system testing, MISR, built-in self test
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Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
By Richard Goering
on May 9, 2012
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning...
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Filed under: Industry Insights, Virtuoso, Analog, IBM, Double Patterning, custom, webinar, Cadence, design rules, digital, modgens, custom/analog, rapid analog prototyping, 20 nm, layout dependent effects, LDE, colorization, Physical Verification System, PVS, color-aware, custom methodology, circuit designers, interconnect, colors, layout designers, Stabenow, Barkley
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Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
By Richard Goering
on May 7, 2012
In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm...
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Filed under: Industry Insights, ARM, encounter timing system, Encounter, EDI, digital implementation, Double Patterning, webinar, 20nm, Cadence, Samsung, extraction, QRC, routing, digital, 20 nm, physical IP, Tan, placement, Encounter Power System, EPS, Lin, LELE, mask misalignment, Physical Verification System, DPT, FlexColor, Cortex-A0, dipole lithography, PVS, mask shift, SPEF, ETS
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Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
By Richard Goering
on May 2, 2012
At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant...
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Filed under: EDA, Industry Insights, ARM, DFM, Encounter, EE Times, Double Patterning, TSMC, Cortex-A15, variability, static timing, Cadence, extraction, FlexModels, 20 nm, PPA, physical IP, ccopt, Desharnais, clock concurrent optimization, LDE, GigaFlex, variation, mask misalignment, test chips, giga-scale, mask shifts, Chong, Quan, 20nm webinar
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DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
By Richard Goering
on May 1, 2012
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27...
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Filed under: Industry Insights, DVCon, low power, TLM, SoC, Accellera, verification, IP, Mixed-Signal, mixed signal, Functional Verification, UVM, SystemVerilog, assertions, SVA, coverage, UVM-MS, debugging, PSL, virtual prototypes, DVCon 2012, covergroups, DVCon presentations, DVCon papers
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How TripleCheck IP Validator Eases Use of Verification IP (VIP)
By Richard Goering
on April 30, 2012
Reusable, commercial verification IP (VIP) has greatly eased the functional verification task for complex interface protocols. However, verification engineers still have a significant amount of manual work to perform. Cadence this week is addressing this...
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Filed under: Industry Insights, Verification IP, VIP, SystemVerilog, Cadence, vPlan, e language, VIP Catalog, PCI Express, PCIe, Hackett, verification plan, coverage database, IP Validator, PureView, coverage model, test suite, PCIe Gen3, TripleCheck, Triple Check
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