DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By Richard Goering
on May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information...
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Filed under: Cadence, chip estimate, ChipEstimate.com, DAC, DAC 2013, Design Automation Conference, IC Design, Industry Insights, IP, IP Talks, IP Talks!, Sean O'Kane, semiconductor IP, silicon IP, SoC
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DAC 2013: User Perspectives on System-Level Verification
By Richard Goering
on May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design...
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Filed under: acceleration, AMD, Cadence, DAC 2013, DAC breakfast, DAC panel, DAC:, emulation, ESL, FPGA prototyping, Frank Schirrmeister, Freescale, IBM, in-circuit acceleration, Incisive, Palladium, RPP, System Design Suite, system to silicon, system-level design, system-level verification, Verification IP, VIP, virtual platforms, virtual prototyping, VSP
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By Richard Goering
on May 13, 2013
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer...
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Filed under: 1801-2009, 1801-2013, Analog, Conformal, Convergence, CPF, CPF user, Functional Verification, Haqqani, IEEE 1801, Incisive, Kamran Haqqani, low power, Maxim, mixed-signal verification, power formats, UPF, UPF 2.1, verification, Virtuoso
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Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story
By Richard Goering
on May 5, 2013
There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in 1988, becoming the largest EDA company within just...
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Filed under: Cadence, company story, Costello, EDA Consortium, EDA startups, EDAC, emerging companies, entrepreneurs, Hogan, Industry Insights, Jim Hogan, Joe Costello, Oasys, Orb Networks, painkillers, slides, VCs, venture capitalists
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Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
By Richard Goering
on May 1, 2013
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation...
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Filed under: AAE, Advanced Analysis Engine, Avago, Benzel, buffering, CDN Live, CDNlive, CDNLive 2013, digital implementation, EDI, EDI 13.1, EDI System, EDI System 13.1, Encounter, GigaOpt, GigaOpt preRoute, Industry Insights, Jack Benzel, layer selection, optimization, path balancing, path compaction, re-buffering, route-driven optimization
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EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
By Richard Goering
on April 29, 2013
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to...
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Filed under: 14nm, 16nm, 20nm, body effect, BSIM-CMG, capacitance, Cgd, Cgs, Cgx, Dey, Dillinger, EDA, EDPS, fin profile, FinFET, FinFET extraction, FinFets, gate input capacitance, Nenni, Oracle, parasitic capacitance, parasitic extraction, planar transistors, RC, Rd, resistance, Rs, Semiwiki, SPICE, transistors
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GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
By Richard Goering
on April 29, 2013
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture...
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Filed under: 10nm, advanced node, Cadence, CDN Live, CDNlive, design technology co-optimization, Double Patterning, DTCO, FinFET, GlobalFoundries, Jongwook Kye, Kye, LELE, LFLE, lithography, multiple patterning, OPC, RET, SADP
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Cadence DAC 2013 and Denali Party Update
By Richard Goering
on April 25, 2013
A very special Design Automation Conference (DAC) will take place in early June - it's the 50 th anniversary of this conference, which has long been a focal point of the EDA industry. This year Cadence is celebrating its 25 th anniversary and has...
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Filed under: Austin, Cadence at DAC, Cadence Theater, DAC, DAC 2013, DAC microsite, Denali Party, Design Automation Conference, Industry Insights
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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment
By Richard Goering
on April 23, 2013
3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013...
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Filed under: 2.5D, 3D, 3D die stacks, 3D IC, 3D stacking, 3DIC, 3D-IC, Brandon Wang, Cadence, design rules, EDI, EDPS, Electronic Design Processes, Encounter, extraction, foundry, Gary Smith, Herb Reiter, HMC, HMCC, hybrid memory cube, IC/package co-design, Industry Insights, Mentor, Micron, OSAT, Power, redundancy, silicon interposer, stress, thermal, TSV, TSV modeling, yield
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Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
By Richard Goering
on April 21, 2013
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack...
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Filed under: Adapt IP, applications, Bois, Bolsens, Cadence, Co-Design, Docea, drivers, EDA, EDP, EDPS, Electronic Design Processes, electronic system level, ESL, hardware/software, HTML5, HW/SW co-development, IEEE, Industry Insights, low power, Matter, McNamara, middleware, OS, partitioning, Power Modeling, Schirrmeister, SLD, Space Codesign, System Development Suite, system level, system-level, system-level design, thermal, Vivado, Wright, Xilinx, zynq, Zynq-7000
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