User Interview: Early Floorplanning Needed For Large Designs
By Richard Goering
on July 29, 2010
Martin Spohr, principal engineer at Renesas Electronics Europe, is working with multi-million gate IC designs with lots of corners and power modes. To deal with this level of complexity, he says, he needs to see the "big picture" of the design...
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Filed under: DAC, Industry Insights: ARM, Renesas, Spohr, floor planning, floorplanning
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How UVM Will Support TLM Design And Verification
By Richard Goering
on July 28, 2010
Cadence last week announced the publication of two books - one about the Universal Verification Methodology (UVM), and one about transaction-level modeling (TLM) design and verification. I noticed that there's a lot of discussion about UVM in the...
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Filed under: Industry Insights, SystemC, High-level Synthesis, TLM, TLM-2.0, verification, e, UVM, SystemVerilog
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Author Roundtable: New TLM Design And Verification Book
By Richard Goering
on July 26, 2010
Cadence last week announced the publication of a new book entitled TLM-Driven Design and Verification Methodology . Available on-line (ordering information and preview here ), the book describes in very practical terms what's needed to implement a...
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Filed under: TLM, verification, Design, McNamara, Bailey, Mosenson, book, roundtable, transcation, Stellfox, Watanabe
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An Embedded Linux To GDSII Flow
By Richard Goering
on July 22, 2010
We've all heard about the RTL-to-GDSII flow. Lately there's been discussion about a TLM (transaction-level modeling) to GDSII flow. How about embedded Linux to GDSII? Such a concept is implied by a newly announced collaboration between ARM and...
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Filed under: Industry Insights, ARM, SoC, IP, EDA360, IP stack, system realization, embedded, collaboration, Linux
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User Interview: Easing Analog/RF IP Creation And Integration
By Richard Goering
on July 21, 2010
Analog and RF IP creation isn't easy in this era of rising complexity and shrinking process nodes. Supporting the integration of IP into SoCs poses many difficulties as well. Jacob Rael, senior manager at Broadcom , is an analog/RF designer who knows...
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Filed under: Industry Insights, DAC, Analog, IP, broadcom, AMS, RF, Rael
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How IBM Supports Parallel HW/SW Development
By Richard Goering
on July 19, 2010
People have been talking about hardware/software co-development for years. IBM is actually doing it - right now - and has managed to reduce overall development times by as much as 50 percent, according to Martin Bakal, marketing manager for the electronics...
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Filed under: DAC, verification, IBM, Incisive, Co-Design, EDA360, SysML, codesign, co-development, software, hardware/software, Tivoli, co-verification, hardware, Bakal, Rational
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Q&A: Mark Gogolewski On Denali History, Acquisition, And IP Trends
By Richard Goering
on July 15, 2010
Mark Gogolewski was a co-founder, CTO, and CFO of Denali Software prior to that company's recent acquisition by Cadence . He is now vice president of R&D of the Front End Group at Cadence. In this interview, he talks about Denali's history...
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Filed under: Industry Insights, verification, IP, DAC DFM, VIP, EDA360, Denali, registers, memories, PCI, memory, DDR, Gogolewski
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User Interview: Verification And Integration Of Analog IP
By Richard Goering
on July 14, 2010
Cambridge Analog Technologies is a provider of high-performance, high-precision, ultra low-power analog IP that is sold to designers of mixed-signal SoCs. It is challenging to design and verify this kind of IP in the first place, and the company faces...
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Filed under: DAC, SoC, Analog, IP, Mixed-Signal, mixed signal, EDA360, Gulati, Cambridge
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User Perspective: What Changes When SoCs Move To 40 nm
By Richard Goering
on July 12, 2010
What are the "gotchas" as design teams move to 40 nm process nodes and below? The best way to find out is to hear from someone who's been there. At Management Day at the recent Design Automation Conference, Jitendra Khare, director of central...
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Filed under: Industry Insights, DAC, SoC, IP Evaluation, AppliedMicro, Management Day, 40 nm, Khare
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Brian Bailey: Building Towards A Cohesive ESL Flow
By Richard Goering
on July 6, 2010
Plenty of niche tools fall under the electronic system level (ESL) label, but putting them together into a cohesive flow has been elusive. At the recent Design Automation Conference, consultant Brian Bailey (and blogger at techbites.com ) described how...
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Filed under: DAC, ESL, SystemC, High-level Synthesis, HLS, TLM, IP, Virtual platform, virtual prototype, EDA360, Brian, Bailey
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