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Functional Verification Blog

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. Then they can add new functionality on...  Read More »
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Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week’s guest blogger] Often we want to re-run a simulation with the exact same random seed that was used in the previous one. Unfortunately far too many people (ok, maybe...  Read More »
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Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models...  Read More »
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A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against...  Read More »
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Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming Universal Verification Methodology (UVM) standard from Accellera, I have seen a couple of references along the lines of "UVM=OVM+VMM" and that really concerns me...  Read More »
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Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture. Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability...  Read More »
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Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave setup for automatically restarting the simulation? If not, this tech tip is for you! Here is the process: Step 0 – Once you are happy with your waveform setup, don’t...  Read More »
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Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption

TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers to learn new techniques and methodologies, or at least provide a solid reference flow to try out new releases of the tools or to be able to compare releases on...  Read More »
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Changing The "F" in RTFM to "Fantastic"

Talk about unsung -- tech writers just don't get the credit they deserve. They sit between R&D, customers, and support trying to capture the capabilities and intent of the software and present it accurately and succintly. They record the "...  Read More »
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AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders...  Read More »
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