An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog
By Tom Anderson
on February 5, 2010
In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. Then they can add new functionality on...
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Filed under: Functional Verification, OVM, VMM, accellera, uvm, methodology, compatibility, OVM 2.1
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Tech Tip: Easy Way To Re-Run Using The Same Seed
By Team Specman
on February 5, 2010
[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week’s guest blogger] Often we want to re-run a simulation with the exact same random seed that was used in the previous one. Unfortunately far too many people (ok, maybe...
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Filed under: Specman, IES-XL, Funcional Verification
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Low-Power Verification With SystemC - The Great Unknown
By Team genIES
on January 28, 2010
Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models...
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Filed under: Functional Verification, IES, SystemC, ESL, Low-power, CPF, UPF
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A Look Back On 2009 (Before Hazarding Predictions For 2010)
By Joseph Hupcey III
on January 28, 2010
Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against...
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Filed under: Functional Verification, SystemVerilog, metric driven verification (MDV), coverage driven verification (CDV), multi-language, SystemC, e, C, EDA, MDV, ESL
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Why UVM Does Not Equal OVM Plus VMM
By Tom Anderson
on January 27, 2010
In the numerous tweets, blog posts, and online forum discussions on the upcoming Universal Verification Methodology (UVM) standard from Accellera, I have seen a couple of references along the lines of "UVM=OVM+VMM" and that really concerns me...
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Filed under: Functional Verification, OVM, VMM, accellera, uvm, methodology, compatibility, OVM 2.1
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Scalability Made OVM The Ideal Choice For UVM
By Adam Sherer
on January 25, 2010
The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture. Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability...
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Filed under: Functional Verification, Simulation acceleration, OVM, SystemVerilog, e, performance, MDV, OVM ML, uvm
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Tech Tip: Waving Specman Objects in SimVision
By Team Specman
on January 22, 2010
Did you know that you can wave Specman objects in IES-XL *and* also save the wave setup for automatically restarting the simulation? If not, this tech tip is for you! Here is the process: Step 0 – Once you are happy with your waveform setup, don’t...
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Filed under: Functional Verification, e, Specman, IES-XL, debug, SimVision
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Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption
By Team MDV
on January 22, 2010
TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers to learn new techniques and methodologies, or at least provide a solid reference flow to try out new releases of the tools or to be able to compare releases on...
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Filed under: Functional Verification, Plan and metrics management, Verification methodology , Enterprise Manager, metric driven verification (MDV), workshops, Incisive, IPCM, MDV, methodology
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Changing The "F" in RTFM to "Fantastic"
By Team genIES
on January 12, 2010
Talk about unsung -- tech writers just don't get the credit they deserve. They sit between R&D, customers, and support trying to capture the capabilities and intent of the software and present it accurately and succintly. They record the "...
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Filed under: Functional Verification, IES, Kit, IES-XL, Tech Pubs, Incisive
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AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance
By Team genIES
on January 8, 2010
The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders...
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Comments (2)
Filed under: Functional Verification, signal integrity, OVM, SystemVerilog, IES, OVM SV, IES-XL, AMIQ, OVM ML, uvm
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