Tips on Writing Macros in Specman e Language
By Team Specman
on May 22, 2012
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following...
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Filed under: Functional Verification, Specman, verification, Incisive, macros, testbench, simulation, e language, define-as, writing macros
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UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
By Axel Scherer
on May 21, 2012
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador...
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Filed under: Functional Verification, Testbench simulation, Verification methodology , OVM, SoC, eRM, CDV, SystemVerilog, IES, e, Specman, IEEE 1647, hvl, verification, Incisive, MDV, VMM, Vera, uvm, testbench, simulation, coverage, videos, universal verification methodology, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, Questa, VCS, IUS, UVM tutorial, verification tutorial, AVM, video tutorial, URM, cowbell
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The Facts: Why Accelerated VIP Is Needed for SoC Verification
By Peter Heller
on May 15, 2012
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already...
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Filed under: Functional Verification, SystemVerilog, SystemC, VIP, verification, uvm, Palladium XP, simulation, e language, Palladium, verification IP, ACE verification, AVIP, acceleration, simulation VIP, SCE-MI, VIP Catalog, Accelerated VIP, emulation, protocol verification
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DAC 2012 Preview: Focus on Formal and ABV Events and Papers
By Team Verify
on May 14, 2012
In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA) , and Team Verify and our colleagues on the Incisive Verification team will be there in force with detailed briefings, panels, papers, posters, and of course live demos...
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Filed under: Functional Verification, Formal Analysis, DAC, ABV, IEV, formal, IFV, assertions, assertion-based verification, Lego, robot, Rubik's Cube, Design Automation Conference, apps, formal apps, "Coverage Unreachability", User Track, papers, coverage unreachability, bypass verification, DAC 2012, model checking, Incisive Formal Verifier
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Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)
By Team Specman
on May 11, 2012
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have...
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Filed under: Functional Verification, Specman, verification, Incisive, testbench, simulation, e language, Specman garbage collection, memory, Specman data, memory management, memory errors, garbage, garbage collection, managing memory
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Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal Verifier
By Team Verify
on May 8, 2012
This 6 minute video is a quick overview of our formal scoreboard app. Specifically, the video references the same AXI bridge example included with Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV) so you can follow along on your workstation...
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Filed under: Formal Analysis, ABV, IEV, formal, IFV, video, Joerg Mueller, scoreboard, apps, formal apps, formal scoreboard
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UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"
By Axel Scherer
on May 3, 2012
To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have...
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Filed under: Functional Verification, Testbench simulation, Verification methodology , OVM, SoC, eRM, CDV, SystemVerilog, IES, verification, Incisive, MDV, VMM, Vera, uvm, testbench, simulation, coverage, videos, universal verification methodology, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, Questa, VCS, IUS, UVM tutorial, verification tutorial, AVM, video tutorial, Stimulus, URM, cowbell
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My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
By Team Specman
on April 24, 2012
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors...
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Filed under: Functional Verification, Specman, IntelliGen, verification, debug, e language, constraints, Gen debugger, Gen, generation, test generation, constraint not enforced
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Analyzing Error Reports When Specman Crashes
By Team Specman
on April 17, 2012
One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: ---...
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Filed under: Functional Verification, Testbench simulation, signal integrity, eRM, SystemVerilog, e, Specman, OVM e, Aspect Oriented Programming, AOP, EDA, IES-XL, team specman, OVM ML, simulation, e language, specman crashes, stack trace
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Video: “Drive For Innovation” Finds It At Every Turn
By Joseph Hupcey III
on April 16, 2012
With some notable exceptions, too often technology trade press reporting has been as dour as the general world news. However, to EETimes editor Brian Fuller, this negativity was at odds with the inspiring technological advances that were regularly crossing...
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Filed under: innovation, Joe Hupcey III, EE Times, Brian Fuller, UBM Electronics, Avenet Express, Chevy Volt, "Drive for Innovation"
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