Home > Community > Blogs > Functional Verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Functional Verification Blog

Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it...  Read More »
Comments (0)
Filed under: , , , , , , ,
Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions). The main updates of version 1.4 are: UVM-SV library upgrade: This release includes...  Read More »
Comments (0)
Filed under: , , , , , ,
sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of my_event: tcm0()@any is { wait; while TRUE { sync change...  Read More »
Comments (0)
Filed under: , , , , , , ,
e and SystemVerilog: The Ultimate Race

For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language...  Read More »
Comments (0)
Filed under: , , , , , , , ,
Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support in Q1 2014

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies. In this second quarterly blog, let me...  Read More »
Comments (0)
Filed under: , , , , , , , , , , , , , ,
Applying Software-Driven Development Techniques to Testbench Development

Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow customers to validate their testbench in isolation...  Read More »
Comments (0)
Filed under: , , , , , ,
Randomizing Error Locations in a 2D Array

A design team at a customer of mine started out with Specman for the first time, having dabbled with a bit of SystemVerilog. I can't reveal any details of their design, but suffice to say they had a fun and not-so-simple challenge for me, the outcome...  Read More »
Comments (0)
Filed under: , , , , , ,
New Incisive Verification App and Papers at DVCon by Marvell and TI

If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement back on January 13 th that Incisive Formal technology, with our new Trident...  Read More »
Comments (0)
Filed under: , , , , ,
Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package

A package to enable resetting a UVM environment in the middle of a test was contributed to Accellera. Its real world application will be presented at DVCon 2014 by Analog Devices....  Read More »
Comments (0)
Filed under: , , , , ,
Incisive vManager at DVCon - Come See It!

Have you heard the news? There is a new version of vManager announced this week, right in time for DVCon. vManager has been completely re-architected to be a database driven environment, scaling to multiple users and supporting gigascale size designs...  Read More »
Comments (0)
Filed under: , , , , , , , , , ,
View older posts »
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.