Digital Implementation

Adding Custom Shapes and Text is New and Improved in EDI System 11

wally1 — Mon, 14 May 2012 17:00:00 GMT

You may have noticed that in the Encounter Digital Implementation (EDI) System 11 the commands addCustomBox, addCustomLine and addCustomText are no longer in the documentation. These previous commands weren't cutting it when it came to the features customers wanted and were not supported by OpenAccess or database commands like dbGet. So they've been replaced in EDI 11 by the commands add_shape and add_text. I think you will like the expanded features and database support of these new commands over their predecessors. Following are some of the highlights. Note the previous addCustom* commands will still work in EDI 11 but may be disabled in the future.

add_shape

Use add_shape to add custom retangles, polygons and path segments to your design. These shapes are represented as Special Nets (snet) in the database. Use the -net option to specify the net name to associate the shape to. If -net is omitted the shape is assigned the net name _NULL to indicate it is floating. This allows you to still access the shape through database commands (i.e. dbGet).

As you can see below add_shape has significantly more features compared to addCustomBox:

add_shape [-help]
-layer {layerNameOrPointer}
-net {string}]
{-rect {x1 y1 x2 y2} | -polygon {x1 y1 x2 y2 ...xn yn} |
[-pathSeg {x1 y1 x2 y2}
-width <value>
[-beginExt <value> -endExt <value>]]}

addCustomBox layerName x1 y1 x2 y2

Here's an example of adding a rectangle for net VDD on layer M1:

add_shape -net VDD -layer M1 -rect {1 1 25 9}

When adding path segments you can specify begin and end extension values. The extensions can be any positive value which is on the manufacturing grid. Also, paths are center-line based so in the example below X=2.5 is where I want the center of the wire. Here's an example of adding a vertical segment on M1:

add_shape -net VDD -layer M1 -pathSeg {2.5 1 2.5 25} -width 3 -beginExt 0 -endExt 0

Combining add_shape with dbGet leads to some nice automation. For example, say I select the rectangle and path I created above. I can then create a polygon on M3 overlapping them using:

add_shape -polygon [lindex [dbShape [dbGet selected.polyPts -i 0] OR [dbGet selected.polyPts -i 1] \

-output polygon] 0] -layer M3 -net VDD

As I mentioned above these shapes are represented as special nets so you can use commands such as editSelect, editDelete, etc. with them just like other special nets.

Here is an example of how the above shapes are represented in DEF:

SPECIALNETS 2 ;

...

- VDD

+ POLYGON Metal3 ( 50000 18000 ) ( 8000 18000 )

( 8000 50000 ) ( 2000 50000 ) ( 2000 2000 ) ( 50000 2000 )

+ ROUTED Metal1 6000 ( 5000 2000 0 ) ( * 50000 0 )

+ RECT Metal1 ( 2000 2000 ) ( 50000 18000 )

+ USE POWER

;

END SPECIALNETS

Another nice feature of add_shape is it will return the pointer of the new object. For example:

encounter 42> set rectPtr [add_shape -rect {10 10 12 12} -layer M4]

0x2aaab3eb8fd0

encounter 43> dbGet $rectPtr.??

beginExt: 0

box: {10 10 12 12}

endExt: 0

geomType: rect

layer: 0x1a7afa48

net: 0x2aaab3834ef8

objType: sWire

polyPts: {{10 10} {12 10} {12 12} {10 12}}

pts: 0x0

shape: notype

shieldNet: 0x0

status: routed

subClass: {}

width: 2

Lastly, you stream out the objects to GDS just like other special nets.

# streamOut map file:

M1 SPNET 1 0

add_text

Use add_text to add custom text on the desired layer. You can see below add_text has significantly more features than addCustomText had:

add_text [-help]

[-alignment {centerCenter centerLeft centerRight lowerCenter lowerLeft lowerRight upperCenter upperLeft upperRight}]

[-drafting {true false}]

[-font {euroStyle gothic math roman script stick fixed swedish milSpec}]

[-height <value>] -label {string} [-layer {layerNameOrPointer}]

[-orient {MX MX90 MY90 R0 R180 R270 R90}] -pt <x> <y>

addCustomText layerName "text" x1 y1 height

For example, to add text on layer M1:

add_text -label "Hello World!" -pt {1 1} -layer M1

When you add text to a specific layer its visibility/selectability is controlled by both the layer and the overall text control.

You can also omit the layer. When you do this the text is added to the general text layer:

add_text -label "Hello World!" -pt {1 1}

Below is the respective stream out mapping depending on whether the text is on a metal layer or the general text layer:

# Mapping text of a specific metal layer:

M1 TEXT 1 0

# Mapping general text:

text TEXT 2 0

Note: If you specify values for font, height, orientation, or alignment it will not be reflected in the EDI System GUI. EDI will display it in the default values. But these properties are saved for Open Access interoperability with Virtuoso. So if you open the design in Virtuoso you'll see the text displayed as you specified.

Brian Wallace

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

Kari — Tue, 01 May 2012 19:41:00 GMT

No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look at are the "results" text file and the ir_limit.gif (at least those are the first ones I look at). While these will give you the immediate information you're looking for regarding the analysis (IR-drop, EM, etc.), several releases ago there appeared a Reports directory which gathered a lot of other information to make your life easier!

Even if your IR-drop looks good, you may still have a few unconnected instances, or be missing a powergrid view, or may have had a problem with the power consumption run that the rail analysis uses. If you know what files to check out in this Reports directory, you can make sure that you're not missing anything. I'll use "VDD" in the filename examples, but of course it could be "VSS," "VDDCore," or whatever your rails are named. Here's my breakdown of what to check out:

VDD.disconnected_inst.asc - This file lists the instances in the design that are not connected to the rail being analyzed. This file MUST be reviewed. There may be cells in this file that you can ignore, such as I/O cells if the LEF files do not model the pwr/gnd busses correctly. In that case, you just need to double-check that these cells are indeed getting power in the design, and make sure that the LEF pin connectivity is the reason they end up here. Once you've done that, you can easily manipulate the file to get rid of the cells you know are false violations and make sure there is nothing else.

VDD.disconnected_pgv.asc - This file will list the cell types whose powergrid views are not connected to the pwr/gnd net you analyzed. This file MUST be reviewed. Some of the cells listed here may be ok - there could be a macro connected to a different power net than the one analyzed, or the same kind of LEF pin issues that are ok to ignore in the disconnected_inst file. But like the disconnected_inst file, make sure you take a look at each item and understand why it's here.

VDD.missing_pgv.asc - This file lists the cells in your design that do not have a powergrid view. This file MUST be reviewed. Looking at this file enabled me to catch a mistake: my design had started using a few new RAM cells, but I had not regenerated the RAM powergrid views. Once I saw the results of this file, I realized I had to generate powergrid views for the new cells and then rerun the power and rail analysis.

VDD.pwr_annotation.asc - This file lists the instances that do not have power consumption information for the rail you analyzed. This file MUST be reviewed. If something went very wrong with the power analysis before the rail analysis, you could catch it here. But there also may be cells listed here that you can ignore: an example would be a PLL instance, that attaches to VSS and VDDA, but you were analyzing VDD. Since this instance does not connect to VDD, the power analysis that was run before rail analysis does not have any power consumption for VDD for this cell.

VDD.pgv_table.asc - This file lists each cell type and what kind of powergrid view was used (port, detailed, etc.), and more importantly, if the powergrid view was NOT used. Any cell types that say "disconnected" here will be in the disconnected_pgv file.

VDD.unconnected_sections.asc - This file lists floating metal segments that are labeled as the pwr/gnd net you analyzed, but are not connected to the grid. Leaving these in the design may not be an issue, but it's a good idea to clean them up so that they don't mask any real issues.

VDD.layerbased_ir.asc - This file is a breakdown of the IR-drop by layer. If you do have an IR-drop issue, you may be able to quickly narrow it down to one layer by looking at this file. If your IR-drop passes, it's still interesting information to have.

This is not an exhaustive list of all the files in the Reports directory; just the ones that I have found to be most useful. Please let me know in the comments if there are other files here you can't live without and how you use them. I'm interested in how other designers are making use of this information.

- Kari Summers

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

wally1 — Thu, 05 Apr 2012 21:31:00 GMT

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?

Fortunately, the application note on NanoRoute Recommended Options is available to help answer these questions. Many of you are utilizing it already but I wanted to highlight it here because it has been recently updated. If you have not referenced this app note in the past, I highly recommend using it. The app note provides the recommended NanoRoute settings with a focus on 32nm and 28nm design nodes. But it is useful regardless of what process node you're designing at. It covers:

Unnecessary NanoRoute options which are no longer needed for routing using NanoRoute
Post Route double cut insertion
Recommended routing strategies for double cut insertion
Recommended NanoRoute scripts for increased double-cut vias insertion targeting TSMC 28nm
Recommended NanoRoute scripts for increased double-cut vias insertion targeting IBM 32/28nm technologies
NanoRoute debugging options

I personally reference multi-cut via insertion flows on pages 5 and 6 on a regular basis. These flows describe a good, better and best approach providing the options to run concurrent and/or post-route insertion of multi-cut vias.

But multi-cut via insertion only works if you have a proper set of multi-cut vias defined. If you're using one of the major foundries they often will provide a technology LEF file with an optimal set of vias for NanoRoute.

If you are developing your own technology LEF consider using the generateVias flow. This flow is described in Solution 11774588. The generateVias command, introduced in EDI 11, will analyze the VIARULE ... GENERATE DEFAULT rules and the cut layer rules (spacing, width, enclosure, etc.) in the LEF to create the optimal set of vias for NanoRoute. generateVias usage is supported for 40nm and below.

For example, you describe a template for how the vias should be generated:

VIARULE M7_M6 GENERATE DEFAULT
LAYER Metal6 ;
    ENCLOSURE 0.005 0.03 ;
LAYER Via6 ;
    RECT -0.035 -0.035 0.035 0.035 ;
    SPACING 0.14 BY 0.14 ;
    RESISTANCE 5.000000 ;
LAYER Metal7 ;
    ENCLOSURE 0.005 0.03 ;
END M7_M6

Then prior to NanoRoute run generateVias to optimal vias:

restoreDesign ...
generateVias
routeDesign

I hope this helps you achieve routing success!

- Brian Wallace

Collaboration, Concurrency, and Convergence: CDNLive! Silicon Valley 2012

BobD — Mon, 19 Mar 2012 20:00:00 GMT

I was out in San Jose last week for CDNLive! Silicon Valley 2012 -- our US user's group conference. I feel like we've been on a good run with this conference during the past few years. I'm seeing users return to present papers year after year. And each year we seem to have new users who are inspired to share what they've been working on at a future conference.

Here are three themes I noticed at this year's conference:

Collaboration

The conference is all about collaboration -- a theme well represented in the keynote speeches. Rick Cassidy from TSMC said that "deep partnership with folks like Cadence sits at the heart of what we need to do." Furthermore, in remarks directed at atttendees, he said that "we (TSMC) will not compete with you." Tom Lantzsch from ARM said "collaboration and partnership is probably the most critical element for our success." And Cadence CEO Lip-Bu Tan (right) said "We need all the key partners to collaborate with us, from the foundry partners to the IP partners all the way to the software developers." (See listings of blog posts on these keynote speeches at the end of this post).

This idea of collaboration isn't new in the IC design community. But I appreciate how the guys at the top reinforced this message. It set the tone for the user papers which followed the keynotes. And for informal conversations throughout the two day conference.

Personally, this resonated with me because I believe that every interaction with a customer is a chance to improve our solutions, and that if we work together we can achieve great things.

Concurrency

Mobile computing was a common thread through each of the keynotes. Mobile devices present unique challenges to the digital designer: Would you like high performance or low power? Yes is the answer.

Deliverying high performance low power design requires breakthrough concurrent design capabilities.Tom Lantzsch from ARM described how a design team implementing one of their cores pushed performance while reducing power. The final gains that enabled their objectives to be achieved came by leveraging Cadence's Clock-Concurrent Optimization (CCOpt). By concurrently optimizing clock and data signals, CCOpt is able to maximize performance while minizing power consumption. More on CCOpt in this interview with Paul Cunningham -- and more to come in future blog posts. I co-presented a paper with Netronome at this year's conference on the topic.

Convergence

Lantzsch revealed that ARM is looking beyond mobile computing and is pursuing new opportunities in the server, home entertainment, and automotive marketplaces. A few years ago, he cataloged the number of devices in his home with IP addresses and found 23. He re-assessed the count recently and found that the number of devices actually went down a bit in recent years even though a number of new devices were added. The reason for this: Convergence in the number of functions each device performs.

As we look around and see multiple MP3 players, smartphones, and tablets in our homes -- whereas we used to have one or two shared desktop computers -- it's striking how personal this technology has become. The devices have certainly increased the number of functions they perform (MP3 player, GPS, e-reader, and more) but a family has more copies of each device than ever before. The changes we've seen in personal communications devices are just the beginning. As these changes take place in home entertainment and automotive it will be a fascinating space to watch.

We see convergence in the digital implementation space as well. Multiple steps are collapsed into single steps within the Encounter Digital Implementation System each release. Concurrent clock and data. Concurrent base and signal integrity delay. Just as we need to mutli-task as engineers, so do the tools we use to get our jobs done.

My favorite part of CDNLive! is creating connections. There are connections between users working with similar functionality in our tools. And there are connections with the developers and product engineers responsible for architecting and improving the tools in areas our customers interact with.

I'd love it if you subscribed to our Digital Implementation Blogs to be informed of new posts.

Bob Dwyer

Photo by Joe Hupcey III

Blog posts on CDNLive! keynote speeches:

CDNLive! - Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

TSMC CDNLive! Keynote - "We Can Beat Moore's Law"

CDNLive! Keynote - New Horizons for ARM based SoCs

Getting Started with EDI 11 – Be Aware of OS and Design Import Changes So Your Migration Goes Smoothly

wally1 — Mon, 19 Mar 2012 18:00:00 GMT

Hello, and welcome to my first blog! As an application engineer in customer support I use Encounter Digital Implementation (EDI) System on a daily basis. Each day I see new issues, design challenges and problems customers are trying to solve. I hope to share many of the common and more interesting problems and their solutions through my blog.

One of my roles in customer support is to identify and author knowledge content for Cadence Online Support (http://support.cadence.com). So I will highlight some of the top content and best practices for getting the most from our online support site. Lastly, I want to hear from you. Is there specific content you would like to see more of on support.cadence.com? If so, please let me know. I hope you enjoy my blog and now onto my first topic.

I'm really excited about the recent announcement of the release of Encounter Digital Implementation (EDI) System 11. There are a few changes you should be aware of which can trip you up when starting with EDI 11.

OS Support

EDI 11 supports Redhat 5.0 (RHEL 5.) and later. If you try to run on a Redhat 4.0 machine you will receive an error such as:

WARNING: HOST <ccslinux12> DOES NOT APPEAR TO BE A CADENCE SUPPORTED LINUX CONFIGURATION.
For More Info, Please Run '<cdsroot>/tools.lnx86/bin/checkSysConf' <productId>.
/icd/flow/EDI/EDI111/latest.RTM/lnx86/tools.lnx86/fe/bin/64bit/encounter: /lib64/tls/libc.so.6: version `GLIBC_2.4' not found (required by /icd/flow/EDI/EDI111/latest.RTM/lnx86/tools.lnx86/fe/bin/64bit/encounter)
/icd/flow/EDI/EDI111/latest.RTM/lnx86/tools.lnx86/fe/bin/64bit/encounter: /lib64/tls/libc.so.6: version `GLIBC_2.4' not found (required by /icd/flow/EDI/EDI111/latest.RTM/lnx86/tools.lnx86/Qt/64bit/lib/libQtCore.so.4)

Go to support.cadence.com and select Resources - Computing Platforms for more information on OS support for Cadence product.

Design Import Changes

A major update has been made to the Design Import step (see What's New). In earlier versions the netlist and libraries were loaded by running the loadConfig command which read in a config file containing a long list of rda_Input variables pointing to the netlist, libraries, etc. In EDI 11, the rda_Input variables have been replaced by a smaller set of more intuitive and better documented variables. The loadConfig/commitConfig commands have been replaced by the command init_design. A sample import flow is:

set init_lef_file "tech.lef cells.lef"
set init_verilog "top.v"
set init_top_cell "top"
set init_mmmc_file "viewDefinition.tcl"
init_design

We've done our best to make the migration to using init_design as smoothly as possible. The Importing and Exporting Designs Chapter of the EDI System User Guide has been updated on the new design import model.

The easiest way to migrate a design is to save it in EDI 10.1 and restore it in EDI 11. This will automatically convert it to the new format. See Solution 11752118 for details.

If you want to convert your current config file (.conf file) a script was recently published to do this. See Solution 11782334 on how to use conf2init.tcl to convert your config file to the new format for init_design.

If you're a Foundation Flow user the migration is easy, as the Foundation Flow scripts have been updated to set the variables and run init_design based on your setup.tcl file. Just make sure to use the EDI 11 scripts and set "set vars(version) 11.1.0" in your setup.tcl file. See Solution 11781374 for more details.

Lastly, Multi-Mode Multi-Corner (MMMC) is required in EDI 11. Solution 11687186 shows a basic MMMC setup for two delay corners and one mode. The EDI System User Guide has additional details on configuring the setup for MMMC analysis.

I hope this makes your migration to EDI 11 go smoothly and avoids any trip-ups.

Brian Wallace

Five-Minute Tutorial: Selective Blockage In EDI 11

Kari — Mon, 12 Mar 2012 14:00:00 GMT

Today I'd like to highlight one of the new features in Encounter Digital Implementation System (EDI) 11: selective blockage. Everyone has used placement blockages before; most of us have used soft blockages also. (As a quick review, a soft blockage is a placement blockage that will keep blocks and cells from being placed there during placement, but cells may be placed there during any ecoPlace/refinePlace, CTS, or optDesign steps.) This is fine for most purposes, but sometimes we want a little more control over what gets placed in the area of a soft blockage.

To use selective blockages, create your soft blockages as you normally would, then set the following:

setPlaceMode -selectiveBlockage true

Setting this variable to true means that by default, buffers, inverters, isolation cells, and level shifters are allowed to be placed inside the soft blockages, as well as any other cells that you optionally specify. If you wish to specify more cells or instances that you would like to allow in the soft blockages, you set the following:

specifySelectiveBlkgGate -cell masterCellName

or:

specifySelectiveBlkgGate -inst instName

or all in one command:

specifySelectiveBlkgGate -cell masterCellName -inst instName

You can use wildcards to make things easy.

For example, let's say that you have an area that you don't want any functional cells to be placed in, but you do want filler cells to be placed there during your filler cell step. You could do this:

specifySelectiveBlkgGate -cell FILL*

You can also specify cells that you don't want to be placed in the selective blockage:

unspecifySelectiveBlkgGate -cell masterCellName -inst instName

What are some creative uses of selective blockage that you have in mind, or have wished you could do in the past? I'd love to hear some ideas in the comments!

- Kari Summers

Five-Minute Tutorial: Where To Find More Encounter Digital Implementation (EDI) System Tutorials

Kari — Mon, 05 Mar 2012 14:00:00 GMT

We've had some people joining the forum lately that are either brand-new to Encounter Digital Implementation (EDI) system, or are coming back to it after several years away. I thought it would be a good time to highlight some great tutorials for getting started with EDI.

If you're working with EDI 10, check out this solution page:

Encounter Digital Implementation (EDI) System 10.1 Tutorial for Beginners

If you're working with EDI 11, check out this solution page:

Encounter Digital Implementation (EDI) System 11 Tutorial for Beginners

A few points about the EDI 11 Tutorial:

This tutorial uses a generic PDK so it's not necessary to download a separate Artisan library. This generic library is packaged with the tutorial database.
This tutorial uses the new init_design flow with MMMC. (Starting with EDI 11, all designs must use the MMMC mechanism.) I see this being useful for EVERYONE, beginners and experts alike, since this is a major change from previous versions.
Have you found yourself wanting to file a Service Request, but you can't include a testcase because your design is proprietary? Use this generic tutorial database to try to reproduce the problem, and then you can submit it as a testcase for the Service Request.

The goal of these tutorials is to provide a small example of using the EDI System software. It is very basic by design, so it's highly recommended that users attend one of the several EDI System training classes provided by Cadence Educational Services. See the Support and Training page on cadence.com for more information.

Many thanks to our own Brian Wallace for putting these tutorials together and providing details for today's post!
Looking for even more quick training info? See this previous post:

Five-Minute Tutorial: Finding EDI Videos

- Kari Summers

Five-Minute Tutorial: Default Naming Conventions in Encounter Digital Implementation (EDI)

Kari — Mon, 27 Feb 2012 15:07:00 GMT

This is a topic that frequently comes up on both internal and external forums. And the answer is right in the Encounter Digital Implementation System (EDI) User Guide, but unless you already know that, you may not think to look for it there.

At some point, all of us have looked at a timing report, and reviewed the list of cells that EDI added during timing optimization. Then we wondered, "Hmmm. What does that prefix mean?" I'm sure you've seen the prefixes of the form FE_PHC, FE_RC, FE_OFC, etc. They do have specific meanings, and when debugging a timing path, it can be very helpful to know where these cells came from.

The following list is located in the EDI User Guide. It's at the end of the Optimizing Timing chapter, in a section called Default Naming Conventions.

Prefix	Description	Command
FE_MDBC	Instance added by multi-driver net buffering	optDesign
FE_MDBN	Net added by multi-driver net buffering	optDesign
FE_OCP_DRV_C	Instance added by DRV fixing	optDesign
FE_OCP_DRV_N	Net added by DRV fixing	optDesign
FE_OCP_RBC	Instance added by rebuffering	optDesign
FE_OCP_RBN	Net added by rebuffering	optDesign
FE_OCPC	Instance added by critical path optimization	optDesign
FE_OCPN	Net added by critical path optimization	optDesign
FE_OFC	Buffer instance added by rule-based buffer insertion	insertRepeater/optDesign
FE_OFN	Buffer net added by rule-based buffer insertion	insertRepeater/optDesign
FE_PHC	Instance added by hold time repair	optDesign
FE_PHN	Net added by hold time repair	optDesign
FE_PSBC	Instance added by buffer insertion in optDesign -postRoute	optDesign
FE_PSBN	Net added by buffer insertion in optDesign -postRoute	optDesign
FE_PSC	Instance added by postroute setuprepair	optDesign
FE_PSN	Net added by postroute setup repair	optDesign
FE_RC	Instance created by netlist restructuring	optDesign
FE_RN	Net created by netlist restructuring	optDesign
FE_USC	Instance added during useful skew optimization	optDesign

Hopefully this information will help you debug a timing path gone wrong, and prompt you to check out the EDI User Guide!

Here are two previous blogs related to debugging timing in EDI:

Demo: Calling Global Timing Debug for a Single Path

An Interview with Global Timing Debug Architect Thad McCracken

- Kari Summers

Five-Minute Tutorial: Change The Background Color Of EDI

Kari — Wed, 08 Feb 2012 16:39:00 GMT

Today's tutorial could probably be called a One-Minute Tutorial, since it's so quick. This is something that came across our internal expert alias, and I figured it's something that most people may not know about. Did you know that you can change the background color of your Encounter Digital Implementation (EDI) design window?

Here's how. In your EDI session, enter the following command:

   setLayerPreference bg -color {<color_name>|color_value}

For example:

   setLayerPreference bg -color white

To set it back to the default, use:

   setLayerPreference bg -color black

You can also use color values, like #000000 (black), #ffffff (white), #ff0000 (red), etc.

If you prefer to use color names, like I do, how do you know what names are legal? You can find a list in a file called rgb.txt, which for sun4v machines, should be in the /usr/X/lib/X11 directory, and for lnx86 machines, should be in the /usr/X11R6/lib/X11 directory. Ask your favorite IT person if you need help finding this file. I found mine to have some color names to rival that of the local paint store. (Papaya Whip, anyone?)

Why would you want to change the background color of EDI? Well, although most people are used to the black background, some folks might be used to a white background based on other tools they have used, or a white background might be better for printing out a snapshot of the design, depending on how you print or plot. And some folks just like to be unique and have colors different than everyone else. To those people, I say: don't ever change. You are the ones who make the world interesting and fun!

Thanks to Susan Zhao for the original Cadence Online Support solution.

- Kari Summers

Five-Minute Tutorial: Multiple View-Only Windows In EDI

Kari — Wed, 25 Jan 2012 16:09:00 GMT

Have you ever had a situation where you want to compare two (or more) different areas of a design, so you end up zooming in to one area, then to the other area, then back and forth as you look at various objects and layers, trying to recall the differences? Have you ever brought up two separate Encounter Digital Implementation (EDI) sessions to make this easier? Then today's tutorial is for you!

There is a way to bring up multiple view-only windows of your design during your current EDI session. Under the Tools menu, click on Design Viewer. A new view-only window will come up with your design in it. You can start as many Design Viewer windows as you like to make your task easier. You can place them side-by-side and compare different areas of the design quickly and easily.

Now, the most common thing to do when looking over a design is to turn various layers and objects on and off. You will notice that it's a pain to go back to your main EDI window to use the Layer Control panel, so it's worth reminding everyone that the Layer Control Panel can be undocked! Just put your mouse on the Layer Control bar, left-click, and drag the panel outside of the EDI window. Now you can place it wherever you like on your desktop and more easily use your view-only windows.

Like the Design Viewer? You may also be interested in this:

Five-Minute Tutorial: The Encounter Digital Implementation Cell Viewer

- Kari Summers