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DAC 2010 – A “Coming Out” Party For 3D-IC Design

Comments(1)Filed under: Digital Implementation, CSV, 3DIC, DATE, 3D, TSV, PoP, flip chip, stacked die, wirebond

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system companies, IDM's, ASIC/IP vendors and foundries. And, the hottest topic this year definitely was 3D-IC (Stacked Die). Most folks talk about the Denali party, but DAC #47 was indeed a "coming out" party for 3D-IC design, and three events stood out.

The first one was "Hogan's Heroes: What Nightmares will 22nm Bring?" This panel had participants from Qualcomm, Xilinx and D2S, and was chaired by Jim Hogan, Vista Ventures. They discussed and debated how the limits of lithography will impose new rules for designers, and discussed the industry impact. They agreed that the biggest factor they would lose sleep over at 22/20nm is "cost"...not performance, power, time-to-market but "cost." They also pointed out that costs of double-patterning (which is a must at 22/20nm) are orders of magnitude higher than traditional methodologies up until 32/28nm. And, that makes alternative solutions like 3D-IC viable alternatives to achieve the next scale of SoC integration, without having to weather the risks of migrating to advanced process nodes.

The second event was a GSA (Global Semiconductor Association) Birds-of-a-Feather event on 3D/TSV (through-silicon via) with an overwhelming 125+ attendees. Herb Reiter and his team brought together representativies from major foundries, IDMs, EDA/IP vendors, design services and other industry organizations to accelerate 3D design. The open forum and discussion were definitely a right step in that direction to not only ensure good tools for cost-effective 3D designs, but also to minimize risk and shorten time-to-profit for the companies that design and manufacture 3D ICs.

The importance of extending today's 2D tools to handle 3D design was realized, given widespread market acceptance and usageof 3D ICs. Only then will IC and system designers be able to cost-effectively and efficiently integrate multiple 2D SoCs into 3D systems. In addition, in the GSA market survey of semiconductor companies that asked about EDA vendors with 3D/TSV support, it was satisfying to see Cadence (38%) leading the pack (Mentor is 25%, Synopsys is 18%). 

The third event was a panel entitled "3D Stacked Die: Now or the Future?" with speakers from TSMC, Samsung, IMEC and Qualcomm. The good news is that all the panelist companies have already moved beyond traditional 2D design techniques and are utilizing key advantages of the third dimension. These companies might be in different stages of the adoption/deployment curve, but all of them consistently and clearly see a path to fully take advantage of 3D IC design.

Also, the speakers highlighted that the first wave of 3D devices would be hitting the market this year. Actual production designs with real silicon, and in real consumer products! This first batch would primarily have memory on one die and the rest of the SoC on another die. This makes sense since embedded memory takes a large portion of the design, thus growing die-size and decreasing yield. Embedded memory also consumes more power and limits bandwidth, as compared to stacking memory on top of the logic dies.

All in all, the refeshing take-away was that the industry has clearly answered for itself the question: "Is 3D design now or the future?"

The answer is an emphatic "Now."  3D design is certainly happening now and at a rapid pace. And, companies not considering 3D IC design face the risk of missing the boat and being left behind.

Rahul Deokar



By RahulD on June 29, 2010
Forgot to mention, that Cadence's 3D-IC Design capabilities were a key component of the recently announced TSMC Reference Flow 11.0

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