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Blogs

Whiteboard Wednesdays - Verification Made Easy with Memory Models

In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help...  Read More »
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New Technical Resources for Encounter Test Users on http://support.cadence.com

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to...  Read More »
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Highlights from Recent IEEE 802.3 Ethernet Standards Meeting

I wanted to share with you a number of updates from last month's IEEE 802.3 meeting in San Diego, California. Cadence has a comprehensive portfolio of design and verification IP, many of which support the latest Ethernet standards. Here are my observations...  Read More »
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3D-IC Working Group—Tool Support Needed, But “Gaps” May Be Narrowing

Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and methodologies, according to presenters at a recent meeting...  Read More »
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DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied...  Read More »
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Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance...  Read More »
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IoT Focus: Natural User Interface Design Crucial to Success

The Internet of Things demands a new user interface--a natural user interface...  Read More »
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Flash Memory Summit: A New Approach to Storage Processing

Flash memory subsystems require a new type of processor architecture if they're to evolve in the coming years, Cadence's Chris Rowen argues. ...  Read More »
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Designer View – RTL Synthesis Success Strategies at 28nm and Below

RTL synthesis is not a simple pushbutton tool, especially at 28nm and below. In a recorded presentation at the Cadence web site Ramesh Rajagopalan, chip lead for physical implementation of networking SoCs at Cisco Systems, shares some of his company's...  Read More »
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Whiteboard Wednesdays - How to Support Higher Performance Multimedia Applications on Hosted Virtual Desktops

In this week's Whiteboard Wednesdays, Charles Qi continues his discussion on hosted virtual desktop applications, explaining how a growing number of users are increasing the demand for higher performance multimedia and user input processing....  Read More »
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