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Custom IC Design Blog

EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take" between the EDA world and the many universities around the world....  Read More »
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Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online Support

Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40 ) LVS Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files. Videos 2. Mismatch Contribution in Virtuoso Analog Design Environment GXL Mismatch...  Read More »
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Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support

Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides and FAQs. Application Notes 1. Using Annotation Browser with Virtuoso IPVS Learn how to invoke the Annotation Browser and have it always appear docked to a specific location...  Read More »
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High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM...  Read More »
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What’s New in Virtuoso ADE XL in IC616 ISR6?

In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3. Here are more new features that are now available in Virtuoso ADE XL in the recently...  Read More »
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Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello...  Read More »
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Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL. Application Notes 1. Physical Verification Checks and Generic...  Read More »
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What's New(-ish) in ADE XL in IC 616 ISR 3?

Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR. These content ISRs receive additional usability testing, product validation, and demonstrations...  Read More »
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Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the...  Read More »
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Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects...  Read More »
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