Home > Community > Blogs > Bloggers
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Meet the Bloggers 


Nebabie
I graduated with a MSEE from University of Southern California in Communications System Design. My first job out of school was analog circuit design. After a 2 year stint I crossed the bridge to the digital world designing IC., but found myself gravitating to analog design methodology.
Recent Posts
See Cadence RF Technologies at IEEE International Microwave Symposium 2014
View all posts »
Parag Bhatnagar
Recent Posts
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
View all posts »
Paul Foster
Recent Posts
Fred Discovers 1000x-10000x Speedup Using wreal Models
How Fred Discovered Mixed-Signal Behavioral Modeling
View all posts »
PaulaJones
Joined Cadence after almost 11 years as Director, Corporate Communications, Tensilica. Previous had own consulting business and was Director of Corporate Communications at MMC Networks, Synopsys, Cirrus Logic, and VLSI Technology.
Recent Posts
How Do You Build a Wi-Fi 802.11ac Programmable Modem?
IP at DAC? You Bet!
View all posts »
Pete Hardee
Joined Cadence in 2010, after 16 years in EDA including time at Synopsys and CoWare. Currently have marketing responsibility for Cadence's low power solution.
Recent Posts
New Incisive Verification App and Papers at DVCon by Marvell and TI
Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
View all posts »
prash
Recent Posts
View all posts »
Qi Wang
Recent Posts
Mixed-signal and Low-power Demo -- Cadence Booth at DAC
Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard
View all posts »
Qingyu Lin
Recent Posts
CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)
View all posts »
Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets.
Recent Posts
The Challenge of System Integration and Bring-Up
Why the Demand for Acceleration and Emulation is Growing
View all posts »
Richard Goering
I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.
Recent Posts
Q&A: From Customer to R&D Director of FPGA-Based Prototyping
PCB West 2014: IPC-2581 Data Transfer Format Links Design, Manufacturing
View all posts »
Sandeep Gor
I am a Staff Application Engineer supporting different functional verification products like Specman, IUS, IMC, vManager. I've 13 years of experience in Functional Verification ranging from block to sub system to SoC level and in eRM and UVM. I have also started looking into System Level verification and it's challenges. Solving the problems with different approaches always excites me !!!
Recent Posts
View all posts »
SarahAdams
Recent Posts
View all posts »
scottj05
Recent Posts
Challenges and Applications in a 3D World
View all posts »
Seow Yin Lim
Recent Posts
IoT Focus: IoT Applications Require a New Architectural Vision
IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT
View all posts »
Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.
Recent Posts
Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online Support
Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online Support
View all posts »
Steven Brown
Recent Posts
Virtual Flash Memory Gets Real
Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!
View all posts »
Steven Lewis
Steve was born and raised in San Jose, CA. After starting with Daisy Corporation (a founder in the EDA industry) for two years, Steve joined Cadence in 1990. Most of his employment with Cadence has been dedicated to the Virtuoso custom design platform. He has held several positions including customer education trainer, field AE, product engineer and today as the Marketing Director for the Virtuoso front-end design and analysis tools.
Recent Posts
EDA Plus Academia: A Perfect Game, Set and Match
What Your Circuit Doesn't Know, Can Kill It!
View all posts »
Sumeet Aggarwal
I have been working in EDA since 2000. After supporting Cadence customers on Functional Verification Platform for initial 11 years, I moved to Cadence Online Support where my job is to ensure we have good collateral and self-help content on Functional Verification, System Design and Verification, Front-End Design and IP technologies and tools.
Recent Posts
The webinar on “Effective system-level coverage” does an effective coverage of the talk
Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption Kits
View all posts »
Tawna Wilsey
Currently a Sr. Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group.
Recent Posts
Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!
How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)
View all posts »
Team ESL
The "Team ESL" blogging core team is:
Recent Posts
Creating SystemC TLM-2.0 Peripheral Models
Understanding Latency versus Throughput
View all posts »
Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:
Recent Posts
How-to Plans for ECOs - Advice From Experts
Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
View all posts »
Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...
Recent Posts
Update to the OVM Register Package
Infinite Playbook for the Verification Superbowl
View all posts »
Team OrCAD
TeamOrCAD is a group of people passionate about OrCAD, the OrCAD brand, and OrCAD-related technologies. Our mission is to proliferate the OrCAD brand and promote awareness of all things OrCAD.
Recent Posts
Cadence OrCAD Capture Marketplace -- The Cool Factors
Economic Recovery on the Way to the Airport
View all posts »
Team Specman
The "Team Specman" blogging core team is:
Recent Posts
Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components
Implementing User-Defined Register Access Policies with vr_ad and IPXACT
View all posts »
Team Verify
Cadence's "Team Verify" is all about formal, mixed engine, and assertion based verification, all the time!
Recent Posts
DVCon 2013 for Formal and ABV Users
New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now
View all posts »
TeamMDV
We are Team MDV - technologist from around the globe experts in automated plan and metrics based functional verification solutions.
Recent Posts
UCIS Coverage Standard -- Innovation Means Business
Enterprise Planner - CSV Import Tech Tip
View all posts »
Tom Volden
After spending a few years designing ICs, I joined Cadence in 1996 as an applications engineer and discovered that I enjoyed and was better suited to the EDA side of IC design rather than design itself. I've since spent time in various roles including applications engineer, Core Competency engineer, and product engineer. I enjoy working with customers to optimize their tool usage and translating their requirements into specs for new feature development.
Recent Posts
What’s New in Virtuoso ADE XL in IC616 ISR6?
What's New(-ish) in ADE XL in IC 616 ISR 3?
View all posts »
tomhackett
Recent Posts
View all posts »
umery
Recent Posts
How Can You Continue Learning About Advanced Verification at Your Desk?
View all posts »