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 Meet the Bloggers 


Joseph Hupcey III
I am a product management director supporting our Silicon Realization product line via Formal and multi-engine verification tools and methodologies. Before going over to "the dark side" (marketing), I worked as an EE in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. I have been a marketing guy for over 10 years now, including a stint in consumer electronics (anyone remember the Handspring "eyemodule"?) before returning to the EDA world.
Recent Posts
DVCon 2013: Functional Verification Is EDA’s “Killer App”
2013 CES: Top 4 Trends Benefiting EDA
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Juergen Jaeger
Recent Posts
Yes We Can...Do FPGA-Based Prototoyping
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Kari Summers
I've worked in Cadence Design Services since June 1997. I've learned a lot and met many great people along the way! I really enjoy helping people with their designs.
Recent Posts
Five-Minute Tutorial: Start the New Year with Voltus
Five-Minute Tutorial: EM Model Files Revisited
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Kishore Karnane
Product Management Director in the Advanced Verification Solutions group at Cadence focusing on advanced verification products like Debug and Digital-centric Mixed Signal Verification. Cadence employee for over 19 years with backgrounds in analog, mixed signal and board level design and IC/SoC verification products and methodologies.
Recent Posts
Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year
Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!
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Lorenz
Recent Posts
Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL
Fast Yield Analysis and Statistical Corners
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Mladen Nizic
over 20 years EDA experience in mixed-signal area
Recent Posts
Mixed Signal Technology Summit Proceedings Now Available
How to Design Analog/Mixed Signal (AMS) at 28nm
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Moshik Rubin
Recent Posts
Cadence Announces Verification IP for MIPI SoundWire™ and C-PHY
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Mukesh
Recent Posts
Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support
11 Things I Learned by Browsing Cadence Online Support
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Naveen Konchada
Recent Posts
Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor
Customer Support Recommended - Dimensioning in Allegro PCB Editor
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Parag Bhatnagar
Recent Posts
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
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Paul Foster
Recent Posts
Fred Discovers 1000x-10000x Speedup Using wreal Models
How Fred Discovered Mixed-Signal Behavioral Modeling
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PaulaJones
Joined Cadence after almost 11 years as Director, Corporate Communications, Tensilica. Previous had own consulting business and was Director of Corporate Communications at MMC Networks, Synopsys, Cirrus Logic, and VLSI Technology.
Recent Posts
See Cadence IP Up Close at the TSMC Symposiums
RealTek Shows New HiFi-based Codec with Software from Sensory and ForteMedia
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Pete Hardee
Joined Cadence in 2010, after 16 years in EDA including time at Synopsys and CoWare. Currently have marketing responsibility for Cadence's low power solution.
Recent Posts
New Incisive Verification App and Papers at DVCon by Marvell and TI
Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
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Peter Heller
Senior Product Line Marketing Manager for System Level Verification IP (VIP) and Interconnect verification at Cadence. With over 20 years industry experience he has played a key role in the growth of Cadence’s VIP business.
Recent Posts
Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration
The Facts: Why Accelerated VIP Is Needed for SoC Verification
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Peter McCrorie
I joined Cadence in 2003 and am currently focused on mixed signal implementation and power integrity analysis. Prior to Cadence, I worked in EDA at Simplex and Mentor Graphics, and prior to my life in EDA, I was designing chips at Philips/Signetics.
Recent Posts
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
EDA Follow-The-Leader ... Signoff In The Design Flow
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Qi Wang
Recent Posts
Mixed-signal and Low-power Demo -- Cadence Booth at DAC
Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard
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Qingyu Lin
Recent Posts
CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)
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Rajendra Pratap
Recent Posts
Bringing Static Analysis Methods to Mixed Signal Designs
Mixed-Signal Physical Design Implementation Made Easy
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Rama Jupalli
Recent Posts
Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in 10 minutes, Now What?
Virtuoso Analog Design Environment XL – Make Friends with Variation
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Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets.
Recent Posts
The Challenge of System Integration and Bring-Up
Why the Demand for Acceleration and Emulation is Growing
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Richard Goering
I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.
Recent Posts
Keynote: EDA “MOOC” Opens Door to a Planet of Talent
“Extreme” Scale EDA Workshop Discusses Research and Funding Priorities
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Rishu Misri Jaggi
Recent Posts
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Robert Dwyer
I'm an Encounter Digital Implementation specialist. I believe every interaction with a customer is an opportunity to improve our solution. I believe we can achieve great things when we focus on a common goal. I type "encounter" every day I'm at work.
Recent Posts
The Case for the Tiny Testcase
How To: Bring Up Encounter "man" Pages from a UNIX Prompt
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Robert Pierce
Recent Posts
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Samir Jafferali
Been fanatically supporting analog/mixed-signal simulation for 9 years and counting. I left my hometown of Montréal, Québec (oui j'parle français) to escape the glacial winters and settle down in toasty Silicon Valley.
Recent Posts
Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL
Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL
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SarahAdams
Recent Posts
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Sathishkumar Balasubramanian
Sathishkumar Balasubramanian has over 12 years of experience in EDA. At Cadence he has held different management positions in services and the sales organization. Currently he is responsible for worldwide mixed-signal solutions marketing at Cadence to promote Cadence’s Industry leading Unified Mixed signal solutions offerings for implementation and verification methodologies. He has extensive design background experience in ASIC design and verification. He holds BS degree in Electronics & Communication Engineering from University of Madras, MS in Computer Engineering from University of Alabama and currently pursuing his MBA from UC Berkeley's Haas School of business.
Recent Posts
Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community
Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events
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Srikanth Vijayaraghavan
Recent Posts
Will Evolving Language Standards Address Mixed-Signal Verification Problems?
Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)
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Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.
Recent Posts
Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support
Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence Online Support
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Steven Brown
Recent Posts
Virtual Flash Memory Gets Real
Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!
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Steven Lewis
Steve was born and raised in San Jose, CA. After starting with Daisy Corporation (a founder in the EDA industry) for two years, Steve joined Cadence in 1990. Most of his employment with Cadence has been dedicated to the Virtuoso custom design platform. He has held several positions including customer education trainer, field AE, product engineer and today as the Marketing Director for the Virtuoso front-end design and analysis tools.
Recent Posts
What Your Circuit Doesn't Know, Can Kill It!
Cadence is the OpenText Connectivity Partner of the Year
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Sumeet Aggarwal
I have been working in EDA since 2000. After supporting Cadence customers on Functional Verification Platform for initial 11 years, I moved to Cadence Online Support where my job is to ensure we have good collateral and self-help content on Functional Verification, System Design and Verification, Front-End Design and IP technologies and tools.
Recent Posts
Learn Logic built-in self-test (LBIST) macro generation and insertion at your desk
Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support in Q1 2014
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Tawna Wilsey
Currently a Sr. Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group.
Recent Posts
Have You Tried the New Transmission Line Library (rfTlineLib)?
SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret!
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Team ESL
The "Team ESL" blogging core team is:
Recent Posts
Creating SystemC TLM-2.0 Peripheral Models
Understanding Latency versus Throughput
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Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:
Recent Posts
How-to Plans for ECOs - Advice From Experts
Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
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Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...
Recent Posts
Update to the OVM Register Package
Infinite Playbook for the Verification Superbowl
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Team OrCAD
TeamOrCAD is a group of people passionate about OrCAD, the OrCAD brand, and OrCAD-related technologies. Our mission is to proliferate the OrCAD brand and promote awareness of all things OrCAD.
Recent Posts
Cadence OrCAD Capture Marketplace -- The Cool Factors
Economic Recovery on the Way to the Airport
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Team Specman
The "Team Specman" blogging core team is:
Recent Posts
Applying Software-Driven Development Techniques to Testbench Development
Randomizing Error Locations in a 2D Array
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Team Verify
Cadence's "Team Verify" is all about formal, mixed engine, and assertion based verification, all the time!
Recent Posts
DVCon 2013 for Formal and ABV Users
New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now
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TeamMDV
We are Team MDV - technologist from around the globe experts in automated plan and metrics based functional verification solutions.
Recent Posts
UCIS Coverage Standard -- Innovation Means Business
Enterprise Planner - CSV Import Tech Tip
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Tianhao Zhang
Recent Posts
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Tom Volden
After spending a few years designing ICs, I joined Cadence in 1996 as an applications engineer and discovered that I enjoyed and was better suited to the EDA side of IC design rather than design itself. I've since spent time in various roles including applications engineer, Core Competency engineer, and product engineer. I enjoy working with customers to optimize their tool usage and translating their requirements into specs for new feature development.
Recent Posts
What's New(-ish) in ADE XL in IC 616 ISR 3?
Efficient Design Migration Using Virtuoso Analog Design Environment GXL
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tomhackett
Recent Posts
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umery
Recent Posts
How Can You Continue Learning About Advanced Verification at Your Desk?
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Vasu Madabushi
Vasu Madabushi is a Senior Product Marketing Manager with the Encounter Digital Implementation team at Cadence
Recent Posts
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
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