 | Abha Maheshwari
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 | Adam Sherer
I market the OVM/UVM, multi-language verification, and low-power simulator for Cadence, tapping 19 years of experience in verification and software engineering including roles in marketing, product management, applications engineering, and R&D. With eight consecutive Boston Marathons run on the Boston Children’s Hospital Marathon Team, I'm always ready to see who has the fastest verification on the planet!Recent Posts |
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 | Alan Whittaker
8 years at Harris Semiconductor in CAD groupRecent Posts |
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 | Andrew Beckett
Application Engineer (and various roles) at Cadence Design Systems since April 1995Recent Posts |
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 | Arthur Schaldenbrand
As a Senior Technical Sales Leader with Cadence Design Recent Posts |
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 | Ashu Vashishtha
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| Benham Farhat
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 | Brad Griffin
16+ years in the bizRecent Posts |
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| David Stratman
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| Deepti Kamal
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| Denali Blog
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 | Frank Schirrmeister
Frank Schirrmeister is Senior Director at Cadence Design Systems in San Jose, responsible for product management of the Cadence System Development Suite, accelerating system integration, validation, and bring-up with a set of four connected platforms for concurrent HW/SW design and verification.Recent Posts |
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 | Gerald "Jerry" Grzenia
Currently a Support Application Engineer working with the Cadence SPB team. I have worked in various roles with Cadence for more than 20 years, with an emphasis on Customer Support and providing detailed product knowledge to both customers and Cadence R&D/Marketing/Sales groups. Recent Posts |
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| Hiroshi Ishikawa
Sr. Engineering Manager, Layout Optimization GroupRecent Posts |
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 | Jack Erickson
Held numerous AE and marketing positions in past 15 years at Cadence, covering simulation, synthesis, physical synthesis, floorplanning, and equivalence checking.Recent Posts |
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 | Jason Andrews
Jason Andrews is an Architect at Cadence Design Systems, where he is responsible for embedded software and hardware/software co-verification products and methodology. He is the author of the book "Co-Verification of Hardware and Software for ARM SoC Design" and lives in Minneapolis with wife Deborah and six wonderful children.Recent Posts |
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| Jim Newton
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 | Joseph Hupcey III
I am a product management director supporting our Silicon Realization product line via Formal and multi-engine verification tools and methodologies. Before going over to "the dark side" (marketing), I worked as an EE in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. I have been a marketing guy for over 10 years now, including a stint in consumer electronics (anyone remember the Handspring "eyemodule"?) before returning to the EDA world.Recent Posts |
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 | Juergen Jaeger
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 | Kari Summers
I've worked in Cadence Design Services since June 1997. I've learned a lot and met many great people along the way! I really enjoy helping people with their designs.Recent Posts |
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 | Marc Greenberg
Marc Greenberg is the Director of Product Marketing for the DDR DRAM Controller and PHY (Memory) IP products at Cadence. Marc's career includes 8 years at Denali and 10 years at Motorola in IP creation, IP management and SoC Methodology roles. Marc frequently publishes articles and makes presentations on DRAM usage, and he represents Cadence at JEDEC.Recent Posts |
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 | Markus Winterholer
Markus Winterholer is working since 2005 for Cadence Design Systems. He is responsible for research and development of embedded software debugging and testing tools. Before he joined Cadence, he worked five years as a freelancer offering consulting services for hardware and software development and verification. Recent Posts |
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 | Mayank Bhatia
Over 9 years experience in supporting, marketing and selling solutions from Cadence. Expertise in stitching up flows to suit end goals.Recent Posts |
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 | Mladen Nizic
over 20 years EDA experience in mixed-signal areaRecent Posts |
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 | Neil Hand
Currently working with end-to-end solutions for customers interested in Power Efficient Design. I have 17+ years of experience in engineering design, customer support, sales and marketing - covering both EDA and telecoms design. Recent Posts |
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| Paul Foster
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 | Pete Hardee
Joined Cadence in 2010, after 16 years in EDA including time at Synopsys and CoWare. Currently have marketing responsibility for Cadence's low power solution.Recent Posts |
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 | Peter Heller
Senior Product Line Marketing Manager for System Level Verification IP (VIP) and Interconnect verification at Cadence. With over 20 years industry experience he has played a key role in the growth of Cadence’s VIP business. Recent Posts |
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 | Peter McCrorie
I joined Cadence in 2003 and am currently focused on mixed signal implementation and power integrity analysis. Prior to Cadence, I worked in EDA at Simplex and Mentor Graphics, and prior to my life in EDA, I was designing chips at Philips/Signetics.Recent Posts |
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| Ping Chen
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 | Prabal Bhattacharya
I have been involved in the development of AMS Simulator for the past 11 years. Specific areas of AMS that interest me are functional verification, assertion in mixed-signal and mixed-signal verification challenges in low-power. I'm also intimately involved with software architecture and refactoring aspects of AMS.Recent Posts |
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 | Qi Wang
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 | Qingyu Lin
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 | Raj Mathur
* Sr. Product Marketing Manager at Cadence Design Systems, Inc.Recent Posts |
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 | Rajendra Pratap
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| Rama Jupalli
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 | Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets. Recent Posts |
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 | Richard Goering
I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.Recent Posts |
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 | Richard Owen
I've been working in EDA for about seven years now, both as an individual contributor and as a team leader. My focus has been on digital design, particularly the challenges faced during synthesis and implementation. Over the past two years, my focus has been enhanced to include all things power related.Recent Posts |
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| Rishu Misri Jaggi
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 | Robert Dwyer
I'm an Encounter Digital Implementation specialist. I believe every interaction with a customer is an opportunity to improve our solution. I believe we can achieve great things when we focus on a common goal. I type "encounter" every day I'm at work.Recent Posts |
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| Robert Pierce
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 | Samir Jafferali
Been fanatically supporting analog/mixed-signal simulation for 9 years and counting. I left my hometown of Montréal, Québec (oui j'parle français) to escape the glacial winters and settle down in toasty Silicon Valley. Recent Posts |
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 | Soheil Modirzadeh
Over 13 years of Marketing experienceRecent Posts |
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 | Srikanth Vijayaraghavan
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 | Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.Recent Posts |
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 | Steven Brown
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 | Steven Lewis
Steve was born and raised in San Jose, CA, getting his BSEE from Santa Clara University in 1987. After working for Daisy Corporation (a founder in the EDA industry) for two years, Steve joined Cadence and has has worked there for 18 years, almost all of that time dedicated to the Virtuoso custom design platform.Recent Posts |
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 | Sunil Gokhale
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 | Tawna Wilsey
Currently a Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group. Recent Posts |
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 | Team ESL
The "Team ESL" blogging core team is:Recent Posts |
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 | Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:Recent Posts |
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 | Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...Recent Posts |
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 | Team OrCAD
TeamOrCAD is a group of people passionate about OrCAD, the OrCAD brand, and OrCAD-related technologies. Our mission is to proliferate the OrCAD brand and promote awareness of all things OrCAD.Recent Posts |
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 | Team Specman
The "Team Specman" blogging core team is:Recent Posts |
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 | Team Verify
Cadence's "Team Verify" is all about formal, mixed engine, and assertion based verification, all the time!
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 | TeamMDV
We are Team MDV - technologist from around the globe experts in automated plan and metrics based functional verification solutions.Recent Posts |
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| Tianhao Zhang
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| Timothy Fahey
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| Vishal Kapoor
Vishal is responsible for marketing for Cadence® SoC Realization business with includes IP and Design Services. In addition, he also is responsible for the strategy and execution of Cadence’s Strategic Business Alliances.Recent Posts |
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 | Xiuya Li
Mr. Xiuya Li is Staff Product Engineer for Analog/Mixed Signal product, specifically for Digital Mixed Signal (DMS) and AMS-Spectre/AMSAPS. Xiuya has been Sales Technical Leader (FAE) in Custom IC group, Technical Field Operations, Cadence Design Systems, Inc. As a pre-sales application engineer, Xiuya supported Analog, Mixed Signal and RF design flow in Cadence Virtuoso Custom Design Platform, including Composer, Analog Design Environment (ADE), Spectre/RF, APS, Ultrasim, AMS Designer, and behavioral modeling with Verilog, VHDL, VerilogA and Verilog AMS. Xiuya has been working in Cadence since Jan. 2002. Prior to Cadence, Xiuya has been an electronics design engineer for 5 years in P.R. China, Republic of Singapore and United States, and he has 2 years’ teaching experience in Electronics Teaching and Research Group in Tsinghua University, Beijing, P. R. China. Xiuya holds BSEE and MSEE degrees from Automation Department in Tsinghua University. He also holds a Master’s Degree in Electrical Engineering from University of Wisconsin – Milwaukee.Recent Posts
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