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 Meet the Bloggers 


Ahmed Elzeftawi
Recent Posts
Library "Safe Margins" -- Are They Really Saving Your Design?
CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
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Andreas Lenz
Sr. Application Engineer at Cadence Design Systems since 2009 at Custom IC.
Recent Posts
IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)
Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes
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Arif Khan
I have over 15 years of design, management, and marketing experience in the semiconductor industry.
Recent Posts
Cadence PCIe Solutions: Configurable, Compliant, and Low Power
Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase
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Arthur Marris
Arthur Marris has three decades of engineering experience in the semiconductor industry.
Recent Posts
Highlights from Recent IEEE 802.3 Ethernet Standards Meeting
Ethernet in Cars - The Next Big Thing for Ethernet
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Arthur Schaldenbrand
As a Senior Technical Sales Leader with Cadence Design
Recent Posts
Measuring Bipolar Transistor ft with Fixed Base-Collector Voltage
Measuring Fmax for MOS Transistors
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Axel Scherer
Axel Scherer is a solutions architect at Cadence Design Systems in Massachusetts, leading the Incisive Product Expert Team for testbenches in general and the Universal Verification Methodology (UVM) in particular.
Recent Posts
My First Internet of Things Device: Moving from a Manual to an Automated Process—Debug Analyzer vs. Simple Logging
Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Display
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Brian Fuller
Reporter, editor and writer for nearly 30 years, most of that in the electronics industry. Past editor in chief of EE Times and EBN and editorial director with UBM. Involved in the Drive for Innovation program in which I drove a Chevy Volt around North America for a year, interviewing engineers.
Recent Posts
ARM Rolls Cortex-M7 Processor for Performance, Power Optimization
Mammals, Insects, and the Data-Efficient Design Imperative
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Bruce Riggins
Recent Posts
Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2
Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2
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CDNS FED GEEK
Recent Posts
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Chinmay Banerjee
Application Engineer
Recent Posts
Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
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Corrie Callenbach
Recent Posts
Whiteboard Wednesdays—Ethernet in Cars
Whiteboard Wednesdays—Selecting the Right PHY Solution
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David Stratman
David Stratman is the RTL Compiler Product Manager and has been a part of the Cadence R&D product management team since 2010. As Product Manger he is responsible for Cadence’s synthesis product strategy & roadmap, driving customer requirements into the RTL Compiler product portfolio and managing their delivery from conception to production shipment.
Recent Posts
8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
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Denali Blog
Recent Posts
Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers
Apple iPad: no LPDDR2?
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Devesh Jain
Recent Posts
Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL
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Frank Schirrmeister
Frank Schirrmeister is Senior Director at Cadence Design Systems in San Jose, responsible for product management of the Cadence System Development Suite, accelerating system integration, validation, and bring-up with a set of four connected platforms for concurrent HW/SW design and verification.
Recent Posts
DAC 2014—ESL Design Is Dead... Long Live ESL!
The Importance of Ecosystems in the Internet of Things Era
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Hiroshi Ishikawa
Sr. Engineering Manager, Advanced Node
Recent Posts
Introduction to Cadence Virtuoso Advanced Node Design Environment
Improved IDF Tool Automatically Fixes Design Rule Violations in Virtuoso
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Hongzhou Liu
Recent Posts
High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma
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Huzaifa Dalal
Chief Fire-starter
Recent Posts
HDMI 2.0 – Ushering in the Next Generation of Ultra HD TV
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Jacek Duda
I have graduated from the University of Economics in Katowice and started my professional career in the marketing department at a credit union. After two years I moved to Evatronix, where I held the position of the Marketing Manager until the company was acquired by Cadence Design Systems, Inc. in June 2013. At Cadence, I hold the position of the Product Marketing Manager for ex-Evatronix IP.
Recent Posts
TSMC 28HPM – Sweet Spot for Today’s Mobile SoCs
M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG
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JDE4
Recent Posts
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Jim Newton
Recent Posts
SKILL for the Skilled: SKILL++ hi App Forms
SKILL for the Skilled: Simple Testing Macros
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JL Gray
Recent Posts
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Juergen Jaeger
Recent Posts
Yes We Can...Do FPGA-Based Prototoyping
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Kari Summers
I've worked in Cadence Design Services since June 1997. I've learned a lot and met many great people along the way! I really enjoy helping people with their designs.
Recent Posts
Five-Minute Tutorial: Start the New Year with Voltus
Five-Minute Tutorial: EM Model Files Revisited
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Kishore Karnane
Product Management Director in the Advanced Verification Solutions group at Cadence focusing on advanced verification products like Debug and Digital-centric Mixed Signal Verification. Cadence employee for over 19 years with backgrounds in analog, mixed signal and board level design and IC/SoC verification products and methodologies.
Recent Posts
Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year
Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!
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Lorenz Neureuter
Recent Posts
Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL
Fast Yield Analysis and Statistical Corners
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Mladen Nizic
over 20 years EDA experience in mixed-signal area
Recent Posts
Mixed Signal Technology Summit Proceedings Now Available
How to Design Analog/Mixed Signal (AMS) at 28nm
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Moshik Rubin
Recent Posts
PCIe Gen4 LIVE Demo at PCI-SIG DevCon Next Week
Cadence Announces Verification IP for MIPI SoundWire™ and C-PHY
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Mukesh
Recent Posts
New Technical Resources for Encounter Test Users on http://support.cadence.com
Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support
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Naveen Konchada
Recent Posts
Customer Support Recommended – Using Test Points in Allegro Design Entry CIS and Allegro PCB Editor Flow
Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor
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Nebabie Kebebew
I graduated with a MSEE from University of Southern California in Communications System Design. My first job out of school was analog circuit design. After a 2 year stint I crossed the bridge to the digital world designing IC., but found myself gravitating to analog design methodology.
Recent Posts
See Cadence RF Technologies at IEEE International Microwave Symposium 2014
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Parag Bhatnagar
Recent Posts
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
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Paul Foster
Recent Posts
Fred Discovers 1000x-10000x Speedup Using wreal Models
How Fred Discovered Mixed-Signal Behavioral Modeling
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Paula Jones
Joined Cadence after almost 11 years as Director, Corporate Communications, Tensilica. Previous had own consulting business and was Director of Corporate Communications at MMC Networks, Synopsys, Cirrus Logic, and VLSI Technology.
Recent Posts
How Do You Build a Wi-Fi 802.11ac Programmable Modem?
IP at DAC? You Bet!
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Pete Hardee
Joined Cadence in 2010, after 16 years in EDA including time at Synopsys and CoWare. Currently have marketing responsibility for Cadence's low power solution.
Recent Posts
New Incisive Verification App and Papers at DVCon by Marvell and TI
Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
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prash
Recent Posts
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Qi Wang
Recent Posts
Mixed-signal and Low-power Demo -- Cadence Booth at DAC
Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard
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Qingyu Lin
Recent Posts
CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)
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Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets.
Recent Posts
The Challenge of System Integration and Bring-Up
Why the Demand for Acceleration and Emulation is Growing
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Richard Goering
I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.
Recent Posts
Cadence Tools, IP Enable First Production TSMC 16nm FinFET System on Chip
IEEE Working Groups Open New Frontiers in Low-Power Design
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Sandeep Gor
I am a Staff Application Engineer supporting different functional verification products like Specman, IUS, IMC, vManager. I've 13 years of experience in Functional Verification ranging from block to sub system to SoC level and in eRM and UVM. I have also started looking into System Level verification and it's challenges. Solving the problems with different approaches always excites me !!!
Recent Posts
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Sarah Adams
Recent Posts
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Scott Jacobson
Recent Posts
Challenges and Applications in a 3D World
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Seow Yin Lim
Recent Posts
IoT Focus: IoT Applications Require a New Architectural Vision
IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT
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Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.
Recent Posts
Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online Support
Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online Support
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Steven Brown
Recent Posts
Virtual Flash Memory Gets Real
Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!
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Steven Lewis
Steve was born and raised in San Jose, CA. After starting with Daisy Corporation (a founder in the EDA industry) for two years, Steve joined Cadence in 1990. Most of his employment with Cadence has been dedicated to the Virtuoso custom design platform. He has held several positions including customer education trainer, field AE, product engineer and today as the Marketing Director for the Virtuoso front-end design and analysis tools.
Recent Posts
EDA Plus Academia: A Perfect Game, Set and Match
What Your Circuit Doesn't Know, Can Kill It!
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Sumeet Aggarwal
I have been working in EDA since 2000. After supporting Cadence customers on Functional Verification Platform for initial 11 years, I moved to Cadence Online Support where my job is to ensure we have good collateral and self-help content on Functional Verification, System Design and Verification, Front-End Design and IP technologies and tools.
Recent Posts
Troubleshooting Incisive Errors/Warnings—nchelp/ncbrowse and Cadence Online Support
The webinar on “Effective system-level coverage” does an effective coverage of the talk
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Tawna Wilsey
Currently a Sr. Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group.
Recent Posts
Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!
How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)
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Team ESL
The "Team ESL" blogging core team is:
Recent Posts
Creating SystemC TLM-2.0 Peripheral Models
Understanding Latency versus Throughput
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Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:
Recent Posts
How-to Plans for ECOs - Advice From Experts
Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
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Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...
Recent Posts
Update to the OVM Register Package
Infinite Playbook for the Verification Superbowl
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Team OrCAD
TeamOrCAD is a group of people passionate about OrCAD, the OrCAD brand, and OrCAD-related technologies. Our mission is to proliferate the OrCAD brand and promote awareness of all things OrCAD.
Recent Posts
Cadence OrCAD Capture Marketplace -- The Cool Factors
Economic Recovery on the Way to the Airport
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Team Specman
The "Team Specman" blogging core team is:
Recent Posts
Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package
Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components
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Team Verify
Cadence's "Team Verify" is all about formal, mixed engine, and assertion based verification, all the time!
Recent Posts
DVCon 2013 for Formal and ABV Users
New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now
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TeamMDV
We are Team MDV - technologist from around the globe experts in automated plan and metrics based functional verification solutions.
Recent Posts
UCIS Coverage Standard -- Innovation Means Business
Enterprise Planner - CSV Import Tech Tip
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Thomas Hackett
Recent Posts
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Tom Volden
After spending a few years designing ICs, I joined Cadence in 1996 as an applications engineer and discovered that I enjoyed and was better suited to the EDA side of IC design rather than design itself. I've since spent time in various roles including applications engineer, Core Competency engineer, and product engineer. I enjoy working with customers to optimize their tool usage and translating their requirements into specs for new feature development.
Recent Posts
What’s New in Virtuoso ADE XL in IC616 ISR6?
What's New(-ish) in ADE XL in IC 616 ISR 3?
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Umer Yousafzai
Recent Posts
How Can You Continue Learning About Advanced Verification at Your Desk?
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