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 Meet the Bloggers 


Adam Sherer
I market the OVM and the multi-language verification simulator for Cadence, tapping 18 years of experience in verification and software engineering including roles in marketing, product management, applications engineering, and R&D. With seven consecutive Boston Marathons run on the Boston Children’s Hospital Marathon Team, I'm always ready to see who has the fastest verification on the planet!
Recent Posts
DVCon: Showcasing The Cadence Passion For Verification Excellence
Scalability Made OVM The Ideal Choice For UVM
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Alan Whittaker
8 years at Harris Semiconductor in CAD group
Recent Posts
RF Measurement Library: Capturing Circuit Characterization Setups on the Schematic
Calculating Large Signal Phase Noise Using Transient Noise Analysis
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Arthur Schaldenbrand
As a Senior Technical Sales Leader with Cadence Design
Recent Posts
Analyzing Distortion With Spectre RF
Periodic Steady-State Analysis for DC-to-DC Converters
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Brad Griffin
16+ years in the biz
Recent Posts
Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support
Come See TeamAllegro at DesignCon2010
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Gerald "Jerry" Grzenia
Currently a Support Application Engineer working with the Cadence SPB team. I have worked in various roles with Cadence for more than 20 years, with an emphasis on Customer Support and providing detailed product knowledge to both customers and Cadence R&D/Marketing/Sales groups.
Recent Posts
What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen!
What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!
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Greg Curtis
I've worked for Cadence since 1989 in various corporate and field roles, but always associated with the Custom IC product line...analog, it's in the blood...
Recent Posts
Analog Behavioral Modeling - What Language Do You Speak?
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Helene Thibieroz
Helene Thibieroz received her B. Tech. and her M.S.degree from the National Institute of Applied Sciences, Toulouse, France and her degree in Doctoral studies in Dept. of Electrical and microelectronics from the Paul Sabatier Scientific University, Toulouse, France in May, 1995.
Recent Posts
DesignCon 2010 Call for Papers
An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso SpectreMDL
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Jack Erickson
Held numerous AE and marketing positions in past 15 years at Cadence, covering simulation, synthesis, physical synthesis, floorplanning, and equivalence checking.
Recent Posts
When Will We Move From RTL to TLM? I Need to Know!
What Can We Learn From The iPad About Chip Design?
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Jason Andrews
Jason Andrews is an Architect at Cadence Design Systems, where he is responsible for embedded software and hardware/software co-verification products and methodology. He is the author of the book "Co-Verification of Hardware and Software for ARM SoC Design" and lives in Minneapolis with wife Deborah and six wonderful children.
Recent Posts
Running Incisive on Ubuntu Linux
Moving Past The Missing Model Syndrome
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John Brennan
Product Marketing Director for Incisive Enterprise Manager (IEM), and Incisive Verification Kit. Involved with functional verification and system design at Cadence since 2002, previously in the systems business doing sales, business development, and marketing.
Recent Posts
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Joseph Hupcey III
I am the marketing director for Incisive Enterprise Simulator, Specman, and the "Trailblazer" program. Before going over to "the dark side" (marketing), I worked as an EE in FPGA design, EDA tools for FPGAs and ASIC CAD, and ASIC verification. I have been a marketing guy for over 8 years now, with a stint in consumer electronics marketing (anyone remember the Handspring "eyemodule"?) before returning to the EDA world.
Recent Posts
DVCon 2010 - Day 3
DVCon 2010 - Day 2
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Kari Summers
I've worked in Cadence Design Services since June 1997. I've learned a lot and met many great people along the way! I really enjoy helping people with their designs.
Recent Posts
Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects
Useful dbGet One-Liners
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Michael Jacobs
I've been at Cadence since 1998 and I've worked in the capacity of design services, applications engineering, and product marketing management supporting digital verification and RTL to GDSII solutions. Prior to Cadence I was a digital design engineer for military hardware.
Recent Posts
Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient
Noise Induced Double Clocking Explained
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Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets.
Recent Posts
Methodology Is Important But Language Matters - Part 2
Methodology Is Important But Language Matters - Part 1
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Richard Goering
I've been writing about EDA and IC design for over 20 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I recently joined Cadence as senior manager of technical communications, and I manage the Industry Insights blog.
Recent Posts
SystemC AMS – A New Proposal For Mixed-Signal Verification
ARM AMBA 4 Protocol And VIP – A Closer Look
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Richard Owen
I've been working in EDA for about seven years now, both as an individual contributor and as a team leader. My focus has been on digital design, particularly the challenges faced during synthesis and implementation. Over the past two years, my focus has been enhanced to include all things power related.
Recent Posts
Cadence and Very Cool Stuff
Leakage Power and National Security
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Robert Dwyer
I'm an Encounter Digital Implementation specialist. I believe every interaction with a customer is an opportunity to improve our solution. I believe we can achieve great things when we focus on a common goal. I type "encounter" every day I'm at work.
Recent Posts
Encounter How To: Writing To/Reading From a File With TCL
User Review of The Encounter Foundation Flow
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Sarah Lynne Cooper Lundell
Many years of experience in EDA covering System-Level Design and Verification. Past related companies include The MathWorks and Verisity.
Recent Posts
The Scoop on the New Incisive Enterprise Verifier
The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume
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Soheil Modirzadeh
Over 13 years of Marketing experience
Recent Posts
Running Low on Power or Receiving Mixed Signals? Talk to the Expert Users
Technical Webinars Hosted by the Experts - Don't Miss Them!
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Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.
Recent Posts
Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements
Things You Didn't Know About Virtuoso: Thumbnails
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Steve Svoboda
Recent Posts
Quiet Before The Storm? And What to Expect at DVCon 2010
We and Our Competitors Agree (Well, Almost!)
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Steven Brown
Recent Posts
What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology Adoption?
Is The Industry Ready For Mainstream Adoption of Higher Abstraction?
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Tawna Wilsey
Currently a Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group.
Recent Posts
Using The Composite Triple Beat Source to Speed up QPSS Analysis
NPORT S-Parameter Model Enhancements
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Team MDV
We are Team MDV - technologiest from around the globe that are able to implement automated plan based verification environments.
Recent Posts
Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption
A Holiday Gift For Verification Projects Adopting MDV
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Team ESL
The "Team ESL" blogging core team is:
Recent Posts
More Details on Post Silicon Embedded Software Verification With ISX
A Classification of ESL - High Level Synthesis Tools
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Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:
Recent Posts
How-to Plans for ECOs - Advice From Experts
Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
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Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...
Recent Posts
Editor For OVM Field Registration Macros
Low-Power Verification With SystemC - The Great Unknown
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Team Specman
The "Team Specman" blogging core team is:
Recent Posts
Built-in Message Logging – Part 2 of 2
Built-in Message Logging – Part 1 of 2
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Tom Anderson
Tom leads marketing for the Open Verification Methodology (OVM) at Cadence and manages the product marketing team responsible for all digital verification software products.
Recent Posts
UVM = OVM 2.1: Even Better!
Have You Considered e Lately?
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