 | Adam Sherer
I market the OVM and the multi-language verification simulator for Cadence, tapping 18 years of experience in verification and software engineering including roles in marketing, product management, applications engineering, and R&D. With seven consecutive Boston Marathons run on the Boston Children’s Hospital Marathon Team, I'm always ready to see who has the fastest verification on the planet!Recent Posts |
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 | Alan Whittaker
8 years at Harris Semiconductor in CAD groupRecent Posts |
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 | Amit Dua
The Product Engineer of Cadence Incisive Enterprise Simulator, Amit is responsible for driving the integration of several key verification technologies, including simulator engine, testbench automation and methodology, in Incisive Enterprise Simulator.Recent Posts |
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 | Arthur Schaldenbrand
As a Senior Technical Sales Leader with Cadence Design Recent Posts |
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 | Bob Hilker
I've been involved with functional verification at Cadence for 18 years. Currently I am a part of the Verification Solutions Deployment team.Recent Posts |
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 | Brad Griffin
16+ years in the bizRecent Posts |
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 | Chi-Ping Hsu
Chi-Ping Hsu is senior vice president of research and development for the Implementation Products Group. In this role, his responsibilities include development of analog design, implementation, and verification; digital implementation and signoff; mixed-signal design and implementation; physical verification; design-for-manufacturing (DFM); and design and analysis of complex PCBs and integrated circuit (IC) packages. Hsu previously served as chief strategist of products and technologies and corporate vice president and general manager of both synthesis solutions and digital IC implementation. During his tenure, Cadence® grew its presence in the synthesis segment tenfold, and the company made significant quality and technology advancements in digital IC implementation. Recent Posts |
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 | Christopher Clee
I began my EDA career in the late 1980s with language-based design pioneers Praxis, working pre and post-sales support for simulation and synthesis products. I then worked for Zuken in various customer-facing roles, supporting PCB design products - specializing in routing. I have spent a total of almost nine years in DFM product marketing at Cadence, punctuated by a two-year stint with a place-and-route startup (thanks, Scott - it was fun!)Recent Posts |
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 | Craig Thompson
I am currently a Sr. Technical Leader (Field Application Engineer) in the North America Central Region primarily supporting the Virtuoso Layout Suite physical design tools and Cadence Space-based Router and Chip Optimizer. My specialty is in CIC advanced automation tool solutions including placement and routing.Recent Posts |
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 | George Frazier
George Frazier is an engineer at Cadence Design Systems where he works on ESL and SystemC tools. He is a past columnist for Windows Developer Magazine and Dr. Dobb's Journal and lives in Lawrence, Kansas with his wife and daughter.Recent Posts |
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 | Gerald "Jerry" Grzenia
Currently a Support Application Engineer working with the Cadence SPB team. I have worked in various roles with Cadence for more than 20 years, with an emphasis on Customer Support and providing detailed product knowledge to both customers and Cadence R&D/Marketing/Sales groups. Recent Posts |
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 | Hany El Hak
I graduated with MSEE degree from Ain Shams University, Electronics and Communications Engineering Department. Ain Shams is the oldest university in the world, located in Cairo, Egypt. The oldest theories of astronomy, engineering and medicine were developed there more than 5000 years ago. My research topic wasn't that old though. My thesis was on Low-Noise Amplifier Design in Advanced CMOS Technology. For several years, I worked as RFIC Designer, wrote six IEEE papers and led RFIC design teams. My last position before I moved to EDA was Design Manager of the RFIC Group at MEMSCAP. Today, I am a Product Marketing Manager at Cadence responsible of RF and Mixed-Signal simulators. Recent Posts |
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 | Helene Thibieroz
Helene Thibieroz received her B. Tech. and her M.S.degree from the National Institute of Applied Sciences, Toulouse, France and her degree in Doctoral studies in Dept. of Electrical and microelectronics from the Paul Sabatier Scientific University, Toulouse, France in May, 1995.Recent Posts |
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 | Hemant Shah
Hemant Shah joined Cadence SPB division in late 2000 as Product Marketing Director for High-Speed Products. Prior to joining Cadence, Hemant was at Xynetix Design Systems, Inc. where he was engineering director for advanced development for 3 years and product marketing director for EDAnavigator, a virtual prototyping tool for PCB systems, for 4 years. Prior to Xynetix, he played various engineering management roles at Intergraph Corporation for 12 years including managing two remote sites in India and Israel. Development of advanced PCB design tools ranged from front end CAE tools [schematic capture, integration of third party tools for Verilog & VHDL design, logic simulation, hardware acceleration from IKOS, ZyCAD; PLD/FPGA tools from Minc, Data I/O and Synthesis tools from AT&T Bell Labs] to PCB layout tools [interactive placement and routing, automatic placement and router]. He holds a B.S. in Electrical Engineering and a M.S. in Computer Science.Recent Posts |
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 | Hiroshi Ishikawa
Sr. Engineering Manager, Layout Optimization GroupRecent Posts |
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 | Jack Erickson
Held numerous AE and marketing positions in past 15 years at Cadence, covering simulation, synthesis, physical synthesis, floorplanning, and equivalence checking.Recent Posts |
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 | Jason Andrews
Jason Andrews is an Architect at Cadence Design Systems, where he is responsible for embedded software and hardware/software co-verification products and methodology. He is the author of the book "Co-Verification of Hardware and Software for ARM SoC Design" and lives in Minneapolis with wife Deborah and six wonderful children.Recent Posts |
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 | Jason Ware
Over 20 years in digital design, synthesis and customer support.Recent Posts |
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 | John Brennan
Product Marketing Director for Incisive Enterprise Manager (IEM), and Incisive Verification Kit. Involved with functional verification and system design at Cadence since 2002, previously in the systems business doing sales, business development, and marketing.Recent Posts |
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| John Pierce
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 | John Wilkosz
John is currently a Core Comp Sr. Technical Leader and has been working for Cadence since 1997 in the Custom IC physical design space. Before Cadence he worked as a circuit and layout design engineer for Atmel. He earned his BSEE from the Rochester Institute of Technology (RIT) and his MSE from the University of Texas at Austin (UT).Recent Posts |
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 | Joseph Hupcey III
I am the marketing director for Incisive Enterprise Simulator, Specman, and the "Trailblazer" program. Before going over to "the dark side" (marketing), I worked as an EE in FPGA design, EDA tools for FPGAs and ASIC CAD, and ASIC verification. I have been a marketing guy for over 8 years now, with a stint in consumer electronics marketing (anyone remember the Handspring "eyemodule"?) before returning to the EDA world.Recent Posts |
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 | Kari Summers
I've worked in Cadence Design Services since June 1997. I've learned a lot and met many great people along the way! I really enjoy helping people with their designs.Recent Posts |
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 | Keith Felton
Over 10 years at Cadence focused on Marketing IC Packaging and SiP technolgies; prior to Cadence spent 3 years at ViewLogic defining the ISIS solution for high-speed topology driven design for PCBs; before that spent 8 years with Racal-Redac (which became Zuken-Redac) in Product Marketing responsible for the Visula PCB solutionRecent Posts |
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| Kenneth Chang
Currently work as Core Comp Technical Leader AE focused on driving frontend design methodology initiatives, including use of advanced synthesis and test with RC (including physical awareness) + ET, Conformal formal verification technologies (of design and SDCs), and ChipEstimate solutions (in-depth technical and $ budget analysis). Previously, I worked as a senior ASIC designer and implementation leader with a number of high profile startups and a large company, developing bullet-proof methodologies and designing a plethora of complex large SOCs with an array of interesting IPs.Recent Posts |
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 | Matthew Bromley
Matt Bromley received his master's of engineering degree with in computer systems and software engineering from the University of York, England, in 1988. He has been employed within the EDA industry for around 20 years and has been involved in the design and development of EDA tools, specializing in data management, process control and collaborations tools. Matt is director of engineering with the SPB division, where he is responsible for the Allegro Design Workbench tools. Recent Posts |
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| Matthew Rardon
Matthew Rardon has served in various capacities at Cadence since 2000 including pre-sales applications engineering and product engineering for such products as RTL Compiler, RTL Compiler Physical, First Encounter, SoC Encounter, Build Gates, Build Gates PKS and Silicon Ensemble. Recent Posts |
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 | Michael Jacobs
I've been at Cadence since 1998 and I've worked in the capacity of design services, applications engineering, and product marketing management supporting digital verification and RTL to GDSII solutions. Prior to Cadence I was a digital design engineer for military hardware.Recent Posts |
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| Michael Kelly
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 | Michael Stellfox
I am the technical leader of the Verification Solutions Architecture Team at Cadence. My team's primary charter is to understand customer verification challenges in order to drive the requirements for the development of the Cadence verification solutions. Recent Posts |
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 | Neil Hand
Currently working with end-to-end solutions for customers interested in Power Efficient Design. I have 17+ years of experience in engineering design, customer support, sales and marketing - covering both EDA and telecoms design. Recent Posts |
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 | Neyaz Khan
Neyaz Khan is an Architect in the Core Comp organization at Cadence. He is involved with the development and deployment of Mixed Signal and Low Power Design & Verification products and methodologies at Cadence. Neyaz has played a key role in the deployment of the Common Power Format (CPF) for Low Power and the Incisive Verification platform at Cadence and has also co-authored books on Advanced Verification using SystemC. Neyaz has over 20 yrs of experience in ASIC Design and Verification. Prior to working for Cadence, he has served in technical-lead roles for a number of companies including Texas Instruments and Bell Northern Research.Recent Posts |
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 | Nigel Bleasdale
I spent 18 years designing mixed signal ASICs, principally in the area of signal conditioning and data recovery before moving into the EDA industry to promote the mixed signal simulation technology. This led me to my current role as a Marketing manager for Virtuoso tools.Recent Posts |
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| Nora Chu
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| Peter McCrorie
I joined Cadence in 2003 and am currently focused on mixed signal implementation and power integrity analysis. Prior to Cadence, I worked in EDA at Simplex and Mentor Graphics, and prior to my life in EDA, I was designing chips at Philips/Signetics.Recent Posts |
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 | Rahul Deokar
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 | Ran Avinun
I am the marketing group director for the System Design and Verification segment at Cadence. I served Cadence/Quickturn in the last 11 years in senior marketing management positions with focus on the acceleration, emulation and system-level markets. Recent Posts |
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 | Richard Goering
I've been writing about EDA and IC design for over 20 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I recently joined Cadence as senior manager of technical communications, and I manage the Industry Insights blog.Recent Posts |
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 | Richard Owen
I've been working in EDA for about seven years now, both as an individual contributor and as a team leader. My focus has been on digital design, particularly the challenges faced during synthesis and implementation. Over the past two years, my focus has been enhanced to include all things power related.Recent Posts |
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 | Robert Dwyer
I'm an Encounter Digital Implementation specialist. I believe every interaction with a customer is an opportunity to improve our solution. I believe we can achieve great things when we focus on a common goal. I type "encounter" every day I'm at work.Recent Posts |
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 | Samir Jafferali
I graduated with a BSEE from Mcgill University in my hometown of Montréal, Québec (oui j'parle français) and escaped the glacial winters to settle down in toasty Silicon Valley. Been fanatically supporting Cadence analog/mixed-signal customers for 7 years and counting.Recent Posts |
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 | Sarah Lynne Cooper Lundell
Many years of experience in EDA covering System-Level Design and Verification. Past related companies include The MathWorks and Verisity. Recent Posts |
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 | Soheil Modirzadeh
Over 13 years of Marketing experienceRecent Posts |
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 | Stacy Whiteman
I've worked in EDA since 1993 (egads--the interwebs had a lot fewer tubes back then) when I found my true calling as an AE after solving a simulation problem for a very grateful customer at 5:30PM on a Friday so he could leave for his vacation. I've worked for Cadence 2X (this time since 2005) as well as several other smaller companies which have since been absorbed into various collectives.Recent Posts |
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 | Steve Svoboda
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 | Steven Brown
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 | Steven Carlson
http://www.linkedin.com/in/stevewcarlsonRecent Posts |
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 | Steven Lewis
Steve was born and raised in San Jose, CA, getting his BSEE from Santa Clara University in 1987. After working for Daisy Corporation (a founder in the EDA industry) for two years, Steve joined Cadence and has has worked there for 18 years, almost all of that time dedicated to the Virtuoso custom design platform.Recent Posts |
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 | Susan Runowicz-Smith
Coordinator Power Forward Initiative,Recent Posts |
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 | Tawna Wilsey
Currently a Staff Support Application Engineer at Cadence Design Systems in the Analog/Mixed-Signal/RF Global Customer Support group. Recent Posts |
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 | Team MDV
We are Team MDV - technologiest from around the globe that are able to implement automated plan based verification environments. Recent Posts |
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 | Team ESL
The "Team ESL" blogging core team is:Recent Posts |
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 | Team FED
Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:Recent Posts |
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 | Team genIES
The engineers that work magic in IES have come together to create Team genIES. Over the next few weeks we'll be adding a few more key contributors but for now...Recent Posts |
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 | Team Specman
The "Team Specman" blogging core team is:Recent Posts |
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 | Thomas Costas
I am a member of the Cadence Virtuoso Product Marketing Team, involved with Virtuoso at the platform and product levels. I bring a background in RFIC design, RF/microwave circuit and system design, EM modeling, device characterization, & RF design techniques. I joined Cadence in 2004 from a fabless semiconductor startup that I co-founded which developed highly integrated single-chip RF transceivers targeting wireless networking in all its forms.Recent Posts |
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 | Thomas Moore
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 | Tom Anderson
Tom leads marketing for the Open Verification Methodology (OVM) at Cadence and manages the product marketing team responsible for all digital verification software products.Recent Posts |
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| Wei Tan
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 | Wilbur Luo
Engineering Group Director in the Manufacturing Models and Implementation DFM groupRecent Posts
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