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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
By Richard Goering
on May 21, 2013
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer...
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Filed under: AMS, analog/mixed-signal, Cadence, Cadence Theater, Cosmic Circuits, custom/analog, customer, DAC, DAC 2013, Design Automation Conference, EDA360 Theater, Forte, Industry Insights, partner, semiconductor IP, SoC, SoC IP, System Development Suite, Tensilica, user presentations, verification
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Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter Features!
By Jeffrey Gallagher
on May 20, 2013
With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it into this list, so that real designers can try them...
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Filed under: 16.6, Allegro Package Designer, APD, APD 16.6, beta releases, beta tools, Digital SiP design, early adopter, feedback, IC Package, IC Package Physical layout and co-design, IC packaging, IC Packaging & SiP design, IC Packaging and SiP, IC packaging documentation, SiP, wirebonding, wirebonds
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What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!
By Gerald "Jerry" Grzenia
on May 20, 2013
Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components...
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Filed under: Allegro, Allegro 16.6, Allegro GUI, Allegro PCB Editor, Grzenia, layout, Overlap components by, PCB, PCB design, PCB Editor, PCB Layout and routing, place replicate, placement edit, Quickplace, SPB
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
By Richard Goering
on May 20, 2013
Cadence today (May 20, 2013) is announcing the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure...
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Filed under: Cadence, distributed processing, encounter timing system, ETS, Molina, Multicore, multi-core, multi-threading, parallel computing, parallel processing, parallelism, parallelized computation, signoff, SSTA, STA, static timing, Tempus, timing analysis, timing closure
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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By Richard Goering
on May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information...
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Filed under: Cadence, chip estimate, ChipEstimate.com, DAC, DAC 2013, Design Automation Conference, IC Design, Industry Insights, IP, IP Talks, IP Talks!, Sean O'Kane, semiconductor IP, silicon IP, SoC
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DAC 2013: User Perspectives on System-Level Verification
By Richard Goering
on May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design...
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Filed under: acceleration, AMD, Cadence, DAC 2013, DAC breakfast, DAC panel, DAC:, emulation, ESL, FPGA prototyping, Frank Schirrmeister, Freescale, IBM, in-circuit acceleration, Incisive, Palladium, RPP, System Design Suite, system to silicon, system-level design, system-level verification, Verification IP, VIP, virtual platforms, virtual prototyping, VSP
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The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
By Jack Erickson
on May 14, 2013
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing....
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Filed under: ASIC, C, C++, C-to-Silicon Compiler, DAC, High-Level Synthesis, hls, Internet, microcontroller, microcontrollers, microprocessors, processors, programmable world, SystemC, the internet of things, TLM, TLM 2.0
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Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
By Stacy Whiteman
on May 13, 2013
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence...
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Filed under: 20nm, AMS, Custom IC Design, custom/analog, layout-dependent effects, mixed signal, Rapid Adoption Kit, Virtuosity, Virtuoso
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By Richard Goering
on May 13, 2013
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer...
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Filed under: 1801-2009, 1801-2013, Analog, Conformal, Convergence, CPF, CPF user, Functional Verification, Haqqani, IEEE 1801, Incisive, Kamran Haqqani, low power, Maxim, mixed-signal verification, power formats, UPF, UPF 2.1, verification, Virtuoso
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What's Good About AMS Data Precision Options? They’re in the 16.6 Release!
By Gerald "Jerry" Grzenia
on May 13, 2013
Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed...
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Filed under: Allegro AMS, AMS, AMS simulation, AMS simulator, Cadence, Cadence Design Systems, design, Grzenia, OrCAD, OrCAD Capture, pspice
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