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SpectreRF at 2013 IEEE/MTT-S International Microwave Symposium in Seattle, Washington
By Tawna Wilsey
on May 23, 2013
If you are attending the International Microwave Symposium ( IMS 2013 ) in Seattle (June 2-7, 2013) stop by the Cadence Design Systems booth, #427. We will be showing new MMSIM12.1.1 features including “Smart” HB GUI, Robust and easy to use...
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Filed under: RF design, Virtuoso Spectre, Spectre RF, Harmonic Balance, spectreRF, RFIC, International Microwave Symposium, shooting newton, Circuit simulation, ADE-L, RF Simulation, Analog Simulation, RF, RF spectre spectreRF, nport, nport settings, HB, analog/RF, Wilsey, MMSIM 12.1
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SKILL for the Skilled: Part 9, Many Ways to Sum a List
By Jim Newton
on May 22, 2013
In the previous postings of SKILL for the Skilled , we've looked at different ways to sum the elements of a list of numbers. In this posting, we'll look at at least one way to NOT sum a list. In my most recent posting , the particular subject...
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Filed under: SKILL, Team SKILL, programming, LISP, SKILL++, IC615, summing, sum a list, Jim Newton, SKILL for the Skilled
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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
By Richard Goering
on May 21, 2013
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer...
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Filed under: Industry Insights, DAC, SoC, verification, AMS, analog/mixed-signal, Cadence, Tensilica, custom/analog, System Development Suite, Design Automation Conference, EDA360 Theater, semiconductor IP, user presentations, Cosmic Circuits, DAC 2013, Cadence Theater, Forte, customer, partner, SoC IP
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Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter Features!
By Jeffrey Gallagher
on May 20, 2013
With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it into this list, so that real designers can try them...
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Filed under: IC Package Physical layout and co-design, Digital SiP design, IC Packaging & SiP design, SiP, APD, IC Packaging and SiP, wirebonds, IC Package, wirebonding, IC packaging, APD 16.6, Allegro Package Designer, 16.6, IC packaging documentation, feedback, early adopter, beta releases, beta tools
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What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!
By Gerald "Jerry" Grzenia
on May 20, 2013
Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components...
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Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, Allegro GUI, Grzenia, Allegro 16.6, placement edit, place replicate, Overlap components by, Quickplace
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
By Richard Goering
on May 20, 2013
Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure...
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Filed under: encounter timing system, SSTA, Multicore, parallelism, static timing, STA, multi-threading, multi-core, Cadence, signoff, ETS, Molina, distributed processing, timing analysis, Tempus, parallel computing, parallelized computation, timing closure, parallel processing
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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By Richard Goering
on May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information...
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Filed under: Industry Insights, DAC, chip estimate, SoC, IP, IC Design, Cadence, Design Automation Conference, IP Talks!, ChipEstimate.com, semiconductor IP, silicon IP, IP Talks, DAC 2013, Sean O'Kane
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DAC 2013: User Perspectives on System-Level Verification
By Richard Goering
on May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design...
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Filed under: Palladium, ESL, virtual platforms, Freescale, AMD, IBM, Incisive, Verification IP, VIP, acceleration, emulation, Cadence, FPGA prototyping, VSP, RPP, virtual prototyping, System Design Suite, system-level design, Frank Schirrmeister, in-circuit acceleration, DAC breakfast, DAC panel, DAC 2013, system-level verification, system to silicon, DAC:
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The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
By Jack Erickson
on May 14, 2013
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing....
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Filed under: C-to-Silicon Compiler, High-Level Synthesis, SystemC, TLM, ASIC, TLM 2.0, DAC, hls, C++, C, microcontroller, the internet of things, microcontrollers, programmable world, processors, Internet, microprocessors
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Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
By Stacy Whiteman
on May 13, 2013
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence...
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Filed under: Custom IC Design, Virtuoso, mixed signal, AMS, custom/analog, Rapid Adoption Kit, layout-dependent effects, 20nm, Virtuosity
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