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Another New Blog on e/Specman
By Team Specman
on July 3, 2009
Specmaniacs rejoice: there is a new blog centered around verification with e /Specman by Sandeep Gor: http://digitalverification.blogspot.com/ Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community! Here are some...
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Filed under: Functional Verification, OVMWorld, e, Specman, IEEE 1647
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Industry Standard SystemC is What Designers Want
By Esteban Svoboda
on July 3, 2009
This past Monday saw not one HLS related announcement but two...this space is really heating-up! Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new...
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Filed under: C-to-Silicon, SystemC, hls, System Design and Verification, ANSI-C
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Inside Cadence: Food for Charity & Freedom
By Joseph Hupcey III
on July 2, 2009
Earlier today at the Cadence San Jose campus, a charity event was held off-cycle from the regular "Stars & Strikes" charity event series , where this time the focus was on food with a hot dog eating contest to benefit for Second Harvest...
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Filed under: Functional Verification, charity benefit, festival, Stars&Strikes
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Flow? What Flow?
By Wei Tan
on July 2, 2009
For EDA software, it seems that it takes just as much effort to develop a methodology to use the software, as writing the tool itself. Ask any CAD group or design group that has to develop their own methodology and you can quickly gauge the many challenges...
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Filed under: Digital Implementation, design closure, EDI system, Encounter digital Implementation system, Foundation Flow
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Alberto Sangiovanni-Vincentelli Q&A: From IC Design To ‘Intelligent Buildings’
By Richard Goering
on July 2, 2009
Alberto Sangiovanni-Vincentelli is a pioneer of the EDA industry, a professor of electrical engineering and computer science at the University of California at Berkeley, and a member of the Cadence Board of Directors. In this interview he talks about...
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Filed under: Industry Insights, ASIC, FPGA, ESL, C-toSilicon Complier, ASSP, IC Design, GSRC
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What's Good About USB 3.0? You Tell Me
By Gerald "Jerry" Grzenia
on July 1, 2009
I read a recent article (June 11, 2009) in EDN magazine - " USB 3.0: A simple Idea Full of Challenges " by Ron Wilson. In a nutshell, Ron says "Super-speed USB ( Universal Serial Bus ) 3.0 sounds like a great idea. Just start with widely...
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Filed under: PCB design, USB 3.0, PHY
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DAC Ecosystem Booth Panels Bring Out User Voice
By Richard Goering
on July 1, 2009
At previous Design Automation Conferences, I’ve always been most interested in what EDA users have to say. One way to hear about the user experience at this year’s DAC is to attend any of five panels at the Cadence Ecosystem Partners booth...
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Filed under: Industry Insights, ARM, DAC, low power, RTL, verification, Mixed-Signal, System C
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Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator
By Bob Hilker
on June 30, 2009
When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer. So much of my time was spent on design and verification, there was little time...
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Filed under: Functional Verification, IES, Incisive Enterprise Simulator (IES), funtional verification, IES-XL, verification, Incisive, SimVision
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Things You Didn't Know About Virtuoso: Which Way Should I "Go"?
By Stacy Whiteman
on June 30, 2009
Just a short post this week, as I've been quite busy recording videos for some of our Virtuoso Platform Webinar Series, the last of which, covering Spec-Driven Design, airs Tues. June 30. Recordings of this and past webinars can be found here . (If...
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Filed under: Custom IC Design, Virtuoso, Virtuoso IC 6.1.3, IC 6.1
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DAC Virtual Platform Workshop
By Jason Andrews
on June 30, 2009
Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC 2009 . Well, now it is too late to start thinking about it, and it is time to start acting by making plans to get to San Francisco. One of the events I will attend is the...
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Filed under: embedded software, virtual platform, DAC, metric-driven verification
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