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Whiteboard Wednesdays—Ethernet in Cars

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing in the Ethernet space—Ethernet in cars. With its high data rate, lightweight cabling, and distributed networking capabilities, as well as the fact that it is an...  Read More »
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Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture) package features the ability to transfer objects from one verification framework to another via multi-language TLM ports. Check out Appendix A if you are a first-time...  Read More »
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IEEE Working Groups Open New Frontiers in Low-Power Design

For many years, electronic designers have struggled to produce low-power chips and systems with tools and standards that focus on register-transfer level (RTL) hardware. After much talk about taking power optimization to higher levels of abstraction,...  Read More »
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Troubleshooting Incisive Errors/Warnings—nchelp/ncbrowse and Cadence Online Support

I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor who I could ask all my queries. But most of the times, I was on my own...  Read More »
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ARM Rolls Cortex-M7 Processor for Performance, Power Optimization

It almost goes without saying: One of the toughest challenges in implementing processor cores is striking that delicate -- sometimes contentious -- balance between performance and power. With that balance in mind, ARM this week (Sept. 24) rolled the latest...  Read More »
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What's Good About Allegro PCB Editor Move Lines/Text to Different Classes? Check Out 16.6!

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved outside their present Class-Subclass structure. In previous releases, workarounds using the clipboard were necessary to accomplish this task. Hover over the line, text...  Read More »
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DVCon Europe 2014—A “First” for Munich, Oct. 14-15

For over 20 years, DVCon (Design and Verification Conference) has been a premier Silicon Valley event for functional IC design and verification. In 2014, for the first time, DVCon is going overseas—for DVCon Europe on Oct. 14-15, as well as DVCon...  Read More »
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Whiteboard Wednesdays—Selecting the Right PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a PHY IP solution. Kishore details topics such as power, performance, and area (PPA), interoperability, DFI, and floorplan flexibilty....  Read More »
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Mammals, Insects, and the Data-Efficient Design Imperative

Cadence IP Group CTO Chris Rowen says cognitive layering and attention to energy optimization are key to IoT system design....  Read More »
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Archived Webinar: Cadence, ARM Forge Design Flow for Mixed-Signal Internet of Things (IoT) SoCs

Many people talk about the Internet of Things (IoT) and how it will affect our work, health, leisure time, communications, and more. As a recently archived webinar shows, Cadence and ARM have gone beyond mere talk and have developed an integrated design...  Read More »
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