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Managing Inherited Connections with CPF in Virtuoso
By Andreas Lenz
on May 23, 2012
Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved...
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Filed under: analog, mixed-signal, mixed signal, CPF, low power, design implementation, Virtuoso, Encounter, oa, Mixed signal physical implementation, Verilog, Virtuoso environment, mixed signal solution, EDI, mixed signal implementation, Common Power Format, mixed signal physical implementation open access, inherited connections, mixed-signal design, OA: OpenAccess
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User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)
By Richard Goering
on May 23, 2012
Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims...
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Filed under: Industry Insights, ARM, Encounter, broadcom, CDNLive!, IR drop, useful skew, CTS, ccopt, clock concurrent optimization, clocking, Azuro, Cortex-A9, CDN Live, timing skew, Lampaert, clock tres synthesis, Koen Lampaert, timing windows
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Things You Didn't Know About Virtuoso: Rapid Adoption Kits
By Stacy Whiteman
on May 22, 2012
This post isn't directly about tips and tricks for getting the most out of Virtuoso, but it is about a new source of information and hands-on guidance to help you put those tips and tricks into action. They're called Rapid Adoption Kits, or--to...
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Filed under: Custom IC Design, Virtuoso, workshop, Constraint-driven, Connectivity-driven, Virtuoso Layout Suite XL, analog, Virtuoso IC6.1.5, Viva, Rapid Adoption Kit, RAKs
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What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to See!
By Gerald "Jerry" Grzenia
on May 22, 2012
Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible...
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Filed under: PCB Layout and routing, PCB design, Allegro, advanced package designer, PCB Editor, APD, IC Packaging, PCB, design, SPB16.5, Allegro 16.5, packaging, Allegro Package Designer, wirebond color, bond wires, visability, color visibility
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Tips on Writing Macros in Specman e Language
By Team Specman
on May 22, 2012
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following...
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Filed under: Functional Verification, Specman, verification, Incisive, macros, testbench, simulation, e language, define-as, writing macros
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UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
By Axel Scherer
on May 21, 2012
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador...
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Filed under: Functional Verification, Testbench simulation, Verification methodology , OVM, SoC, eRM, CDV, SystemVerilog, IES, e, Specman, IEEE 1647, hvl, verification, Incisive, MDV, VMM, Vera, uvm, testbench, simulation, coverage, videos, universal verification methodology, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, Questa, VCS, IUS, UVM tutorial, verification tutorial, AVM, video tutorial, URM, cowbell
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Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
By Richard Goering
on May 21, 2012
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries...
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Filed under: Industry Insights, Si2, SiP, Standards, stacked die, 3D, TSV, GSA, 3D IC, 3D-IC, wide i/o, foundry, Potts, 2.5D, wide io, GSA 3D IC, via, OSAT, thernal, power density, Ken Potts
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Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
By Richard Goering
on May 17, 2012
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new...
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Filed under: Industry Insights, 3D ICs, SoC, Semico, IP, Kapoor, IP quality, system on chip, PCI Express, semiconductor IP, PCIe, silicon IP, 3D-ICs, NVM Express, NVMe, IP subsystems, system-driven IP, Impact, Feldhan, IP ecosystem, design factory
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Measuring 2-Tone Intermodulation Using Envelope-Following Analysis
By Tawna Wilsey
on May 16, 2012
From time to time, SpectreRF users simulate very large, extracted-view circuits in 2+ tone QPSS. In many of those cases, memory requirements exceed the available resources. When that happens and small-signal approximations aren’t applicable, the...
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Filed under: RF design, RF Block Simulation, wireless integrated circuit verification, RF designer, Virtuoso Spectre Simulator GXL, Spectre, Spectre RF, Harmonic Balance, spectreRF, RFIC, MMSIM, RF Simulation, Analog Simulation, ADE, RF, RF spectre spectreRF, envelope, simulation, fast envelope, spectre spectreRF, analog, HB, analog/RF, SpectreRF tutorials
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A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
By Parag Bhatnagar
on May 16, 2012
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else...
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Filed under: mixed-signal, ECOs, signoff, mixed signal, OpenAccess, Virtuoso, Encounter, IC 6.1, mixed signal design, STA, timing model, static timing analysis, oa, ECO, open access, Mixed signal physical implementation, mixed-signal ECOs, parasitic, Virtuoso environment, mixed signal solution, EDI, EDIS, mixed signal implementation, ECOs and PCells
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