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Do Hardcopy Books Still Have Value?
By Tom Anderson
on July 29, 2010
As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just published "A Practical Guide to Adopting the Universal Verification Methodology (UVM).” It is the world’s first book on the UVM. Or is it? The definition...
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Filed under: Functional Verification, Verification methodology , OVM, VIP, VMM, accellera, uvm
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Tech Tip: Dramatically Improve Throughput With “Assertion Distributor”
By Team Verify
on July 29, 2010
There are several ways that Incisive Formal Verifier (IFV) can be set to evaluate properties in parallel. The bottom line is that customers using these “productivity flows” have been dramatically increasing their verification throughput –...
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Filed under: Functional Verification, ABV, IEV, vPlan, IFV, Desktop Manager, Fornal
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User Interview: Early Floorplanning Needed For Large Designs
By Richard Goering
on July 29, 2010
Martin Spohr, principal engineer at Renesas Electronics Europe, is working with multi-million gate IC designs with lots of corners and power modes. To deal with this level of complexity, he says, he needs to see the "big picture" of the design...
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Filed under: DAC, Industry Insights: ARM, Renesas, Spohr, floor planning, floorplanning
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Favorite Features Of An IC Package Designer: Assembly Rule Checks
By Team Allegro
on July 28, 2010
This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the...
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Filed under: IC Package Physical layout and co-design, Digital SiP design, Analog and RF SiP design, IC Packaging & SiP design, wirebond profile library, Kulicke & Soffa, SPB, 3D-IC, SiP, SPB16.3, Allegro 16.3, IC Packaging and SiP, package
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What's Good About Allegro GRE Bundle Editing? SPB16.3 Has Many New Enhancements!
By Gerald "Jerry" Grzenia
on July 28, 2010
The Allegro Global Route Environment (GRE) has expanded its capabilities in the area of bundled editing in the SPB16.3 release. It’s now easier to copy, move, and split bundles. Copy Flow lets you copy the flow path from one bundle to another. Its...
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Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, Allegro, PCB Editor, PCB, SPB 16.3, Allegro 16.3, layout, SPB16.3, GRE, global route
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How UVM Will Support TLM Design And Verification
By Richard Goering
on July 28, 2010
Cadence last week announced the publication of two books - one about the Universal Verification Methodology (UVM), and one about transaction-level modeling (TLM) design and verification. I noticed that there's a lot of discussion about UVM in the...
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Filed under: Industry Insights, SystemC, High-level Synthesis, TLM, TLM-2.0, verification, e, UVM, SystemVerilog
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Things You Didn't Know About Virtuoso: ADE XL
By Stacy Whiteman
on July 27, 2010
I know, it's been a long time since my last post. You see, we've finally arrived at a topic near and dear to my heart -- ADE XL. The reason for my hesitation in approaching this topic is not that it's difficult, but rather that there's...
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Filed under: Custom IC Design, Virtuoso, Virtuoso IC 6.1.3, IC 6.1.4, Virtuoso Analog Design Environment, IC 6.1, ADE, ADE-XL
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Author Roundtable: New TLM Design And Verification Book
By Richard Goering
on July 26, 2010
Cadence last week announced the publication of a new book entitled TLM-Driven Design and Verification Methodology . Available on-line (ordering information and preview here ), the book describes in very practical terms what's needed to implement a...
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Filed under: TLM, verification, Design, McNamara, Bailey, Mosenson, book, roundtable, transcation, Stellfox, Watanabe
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Programatically Capturing Cell Delay In The Encounter Digital Implementation System
By Robert Dwyer
on July 23, 2010
A while back we were talking about how to programatically troubleshoot timing violations in Encounter . That post recieved a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought...
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Comments (1)
Filed under: Digital Implementation, static timing analysis, CTE-TCL, TCL, scripting
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An Embedded Linux To GDSII Flow
By Richard Goering
on July 22, 2010
We've all heard about the RTL-to-GDSII flow. Lately there's been discussion about a TLM (transaction-level modeling) to GDSII flow. How about embedded Linux to GDSII? Such a concept is implied by a newly announced collaboration between ARM and...
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Filed under: Industry Insights, ARM, SoC, IP, EDA360, IP stack, system realization, embedded, collaboration, Linux
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