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Whiteboard Wednesdays—How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design....  Read More »
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Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components

What happens when you have two verification components (for example one implemented in e and the other in System Verilog) and one of the frameworks drops its last TEST_DONE objection?...  Read More »
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Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online Support

Highlights from July and August 2014 for resources related to Cadence Virtuoso and other electronics design tools. ...  Read More »
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Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Display

The Retina display in the Apple MacBook Pro has much more value than I originally expected. As similar observatiom is being made about the Incisive debug Analyzer....  Read More »
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Electromigration – What IC Designers Need to Know

If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in...  Read More »
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IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

Winning in the IoT applications space requires a system-level design mentality and an abiding insight into energy, cost and time-to-market challenges....  Read More »
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Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC Packaging Tools

Normal 0 false false false EN-US X-NONE X-NONE Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the...  Read More »
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What's Good About Allegro Design Workbench Team Collaboration? Find Out in the 16.6 Release

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration: Logical design integrator Responsible for front-end design Physical design integrator Responsible for back-end design A logical...  Read More »
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Whiteboard Wednesdays - USB Controller Connectivity

In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC) and how they improve connectivity...  Read More »
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Challenges and Applications in a 3D World

Confronting the challenges and possibilities of 3D silicon design starts with comprehensive simulation and verification models....  Read More »
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