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Panelists: Bridging the Gap Between Analog and Digital Design
By Richard Goering
on February 1, 2012
Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow...
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Filed under: Industry Insights, SoC, Analog, verification, IP, Mixed-Signal, mixed signal, Panel, AMS, DesignCon, Nizic, Cadence, Synopsys, analog IP, digital, microcontrollers, analog comeback, analog automation, Brian Bailey, analog design, IPextreme, analog panel, Savage, A/MS, Cypress, Tanner
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What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on January 31, 2012
In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application...
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Filed under: PCB Layout and routing, PCB design, Allegro, SI, PCB, PCB SI, layout, PCB Signal integrity, High Speed, Allegro 16.5, signal integrity, 16.5, application mode
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Whitepaper: Verification Performance is More Than Raw Simulation Speed
By Richard Goering
on January 31, 2012
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises...
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Filed under: Industry Insights, Multicore, verification, Functional Verification, Incisive, Simulation, multi-core, whitepaper, assertion-based verification, debugging, simulator performance, RTL simulation, white paper, Incisive Enterprise Simulator, scaling, simulation speed, gate-level simulation, reseeding, elaboration, regressions
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System-Level Design and the Waves of EDA
By Frank Schirrmeister
on January 30, 2012
Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system...
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Filed under: ESL, software, Virtual Platforms, virtual prototypes, abstraction, IP assembly, IP integration, IEEE Spectrum, VSI, Schirrmeister, automobiles, 1997, ESL system-level design, cars, EDAC, VCC
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Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
By Adam Sherer
on January 30, 2012
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these...
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Filed under: Functional Verification, Low Power, Simulation acceleration, IES, Incisive Enterprise Simulator (IES), DVcon, IES-XL, Incisive, Mixed-Signal, Low-power, uvm, testbench, whitepaper, simulation, assertion-based verification, 20nm, Incisive Enterprise Simulator, gate level, gate-level, verification speed, Incisive performance, simulation speed
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Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
By Richard Goering
on January 30, 2012
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore...
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Filed under: Industry Insights, DVCon, low power, TLM, verification, Mixed-Signal, System C, mixed signal, Functional Verification, UVM, NASCUG, emulation, coverage, UVM-MS, debugging, prototyping, mixed-signal verification, DVCon 2012, HW/SW co-verification
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Things You Didn't Know About Virtuoso: We've Got You Cornered
By Stacy Whiteman
on January 26, 2012
One of the big buzzwords around the EDA world these days is "variation." Don't you just love buzzwords? Take a perfectly normal, slightly ambiguous word, capitalize it, add a another slightly ambiguous hyphenated suffix, and suddenly you've...
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Filed under: Custom IC Design, Virtuoso, Virtuoso Analog Design Environment, analog, ADE, ADE-XL, IC 6.1.5, Virtuoso IC6.1.5, custom/analog, Analog Design Environment, Analog Design Environment, IC615, corners, corner analysis
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Video Killed The Reference Manual Star
By Team Verify
on January 26, 2012
[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star " as you read the following] Q: What is your favorite pastime? A: Reading reference manuals! No? Really? OK -- with all due respect to our Tech Pubs team...
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Filed under: Functional Verification, Formal Analysis, metric driven verification (MDV), PSL, SVA, ABV, MDV, IEV, formal, IFV, assertions, ABVIP, simulation, formal verification, assertion-based verification, videos, Assertion-Driven Simulation, YouTube, Axel Scherer
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UVM: "Everything that Can be Invented Has Been Invented" Not True!
By Adam Sherer
on January 26, 2012
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with...
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Filed under: Functional Verification, SystemVerilog, IES, multi-language, Incisive, MDV, Mixed Signal, Mixed-Signal, Low-power, VMM, uvm, Acellera VIP TSC, 20nm, UVM-MS, UVM e
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SPIE Papers Showcase DFM and Lithography R&D
By Richard Goering
on January 26, 2012
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational...
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Filed under: Industry Insights, lithography, DFM, CMP, IP, EUV, Double Patterning, OPC, 28nm, variability, pattern matching, yield, source mask optimization, 20nm, 22nm, Cadence, manufacturability, layout, leakage, LDE, in-design signoff, metal fill, layout-dependent effects, SPIE, computational lithography, SADP, context, model calibration, RET, hotspot
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