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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By Richard Goering
on May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information...
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Filed under: Cadence, chip estimate, ChipEstimate.com, DAC, DAC 2013, Design Automation Conference, IC Design, Industry Insights, IP, IP Talks, IP Talks!, Sean O'Kane, semiconductor IP, silicon IP, SoC
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DAC 2013: User Perspectives on System-Level Verification
By Richard Goering
on May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design...
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Filed under: acceleration, AMD, Cadence, DAC 2013, DAC breakfast, DAC panel, DAC:, emulation, ESL, FPGA prototyping, Frank Schirrmeister, Freescale, IBM, in-circuit acceleration, Incisive, Palladium, RPP, System Design Suite, system to silicon, system-level design, system-level verification, Verification IP, VIP, virtual platforms, virtual prototyping, VSP
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The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
By Jack Erickson
on May 14, 2013
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing....
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Filed under: ASIC, C, C++, C-to-Silicon Compiler, DAC, High-Level Synthesis, hls, Internet, microcontroller, microcontrollers, microprocessors, processors, programmable world, SystemC, the internet of things, TLM, TLM 2.0
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Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
By Stacy Whiteman
on May 13, 2013
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence...
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Filed under: 20nm, AMS, Custom IC Design, custom/analog, layout-dependent effects, mixed signal, Rapid Adoption Kit, Virtuosity, Virtuoso
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By Richard Goering
on May 13, 2013
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer...
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Filed under: 1801-2009, 1801-2013, Analog, Conformal, Convergence, CPF, CPF user, Functional Verification, Haqqani, IEEE 1801, Incisive, Kamran Haqqani, low power, Maxim, mixed-signal verification, power formats, UPF, UPF 2.1, verification, Virtuoso
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What's Good About AMS Data Precision Options? They’re in the 16.6 Release!
By Gerald "Jerry" Grzenia
on May 13, 2013
Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed...
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Filed under: Allegro AMS, AMS, AMS simulation, AMS simulator, Cadence, Cadence Design Systems, design, Grzenia, OrCAD, OrCAD Capture, pspice
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Things You Didn't Know About Virtuoso: Delta Markers in ViVA
By Stacy Whiteman
on May 9, 2013
This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while back who Is a CAD engineer busily supporting a large user community, but had been stumped by the question "How do I create a delta marker in VIVA?" I'm...
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Filed under: Analog Design Environment, Analog Design Environment, Custom IC Design, delta markers, IC 6.1.5, IC615, Virtuoso IC6.1.5, Viva, ViVa-XL
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Mode Support for SimVision “Stop Simulation” Button
By Team Specman
on May 8, 2013
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility...
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Filed under: AF, debug, e language, Functional Verification, IES, Incisive, SimVision, Specman, stop simulation, stop Specman
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New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
By Adam Sherer
on May 7, 2013
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE...
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Filed under: Adam Sherer, CDNLive, CPF, CPF 2.0, DPA, IEEE 1801, IEEE 1801-2009, IES, Incisive, Incisive Enterprise Simulator, low power, low-power, low-power design, power, power shutoff, PSO, UPF, UVM, verification
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What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia
on May 6, 2013
Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS ( Capture ) product has a few new enhancements for Saving designs. Read on for more details ... Save In the Hierarchy viewer...
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Filed under: Allegro, Allegro 16.6, Allegro Design Entry, Cadence Design Systems, Capture, Capture CIS, Capture-CIS, design, Design Entry, Design Entry CIS, Front-end PCB design, Grzenia, SPB
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