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UVM = OVM 2.1: Even Better!
By Tom Anderson
on March 16, 2010
Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face-to-face meeting held last week in Massachusetts. But with the steady stream of tweets coming from several of those who did attend, I almost felt as if I were there...
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Filed under: Functional Verification, OVM, uvm, Accellera VIP TSC
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Bringing MEMS Design To The Mainstream
By Richard Goering
on March 15, 2010
Micro-electrical mechanical systems ( MEMS ) have been around for years, and have found their way into high-volume applications such as automobile air bag controllers, GPS systems, and inkjet print heads. But MEMS devices such as accelerometers, gyroscopes...
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Filed under: Industry Insights, TMSC, Virtuoso, PDK, Coventor, MEMS
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Built-in Message Logging – Part 1 of 2
By Team Specman
on March 11, 2010
[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK] Messaging is important for two main reasons: It is essential for debugging It can greatly impact simulation performance This is why Specman has a messaging infrastructure...
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Filed under: Functional Verification, e, Specman, AOP, IES-XL, tech tips
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What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!
By Gerald "Jerry" Grzenia
on March 10, 2010
You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release These enhancements will improve your experience with analyzing simulation results especially for dense designs. These features include: Easy to...
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Filed under: PCB design, Allegro, AMS simulator, SPB 16.3, AMS
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Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient
By Michael Jacobs
on March 10, 2010
Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to...
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Filed under: Digital Implementation, Signoff Analysis, static timing analysis, Early Rail Analysis, dynamic rail analysis, power analysis, SI analysis, signal integrity, noise analysis, timing system, Multi-Core and Parallel rocessing, timing convergence, Timing Constraints, Timing analysis, Extraction, OCV, Statistical, signoff
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Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements
By Stacy Whiteman
on March 10, 2010
I'm not going to beat around the bush here. I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4. I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that...
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Filed under: Custom IC Design, Virtuoso, IC 6.1.4, Virtuoso Analog Design Environment
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Challenging Misconceptions About Verification Languages
By Richard Goering
on March 10, 2010
One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way...
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Filed under: Industry Insights, DVCon, SystemC, OVM, verification, e, OOP, HVL
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VIP Portfolio Extension: New AMBA 4 Protocol Support
By Team Specman
on March 8, 2010
ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol. Here is the official announcement, which...
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Filed under: Functional Verification, OVM, metric driven verification (MDV), ARM, VIP, Cadence VIP portfolio, vPlan, AMBA, CMS, Compliance Management System
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When Will We Move From RTL to TLM? I Need to Know!
By Jack Erickson
on March 8, 2010
My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point...
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Filed under: Logic Design, Synthesis, RTL, RTL compiler, C-to-Silicon, TLM
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Q&A: New Challenges, New Solutions In IC Implementation
By Richard Goering
on March 8, 2010
Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are...
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Filed under: Industry Insights, DFM, Encounter, CPF, SoC, digital implementation
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