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IBM/Cadence Collaboration Points To “Next Generation” EDA
By Richard Goering
on February 8, 2010
Embedded software development and hardware/software integration have become primary bottlenecks for system-on-chip (SoC) projects. Still, most EDA tools remain exclusively focused on hardware design, while software development tools have no understanding...
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Filed under: Industry Insights, SoC, verification, IBM, Incisive, Enterprise Manager, EVMS
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An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog
By Tom Anderson
on February 5, 2010
In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing OVM 2.1 as is, with full backwards compatibility and without trying to cram overlapping functionaity from VMM into the base. Then they can add new functionality on...
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Filed under: Functional Verification, OVM, VMM, accellera, uvm, methodology, compatibility, OVM 2.1
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DesignCon Panel: “Total” IP Solutions Fuel SoC Integration
By Richard Goering
on February 5, 2010
Panelists at DesignCon Feb. 3 agreed that just shipping RTL code for silicon IP is far from sufficient. But what comprises a “total” IP solution for SoC integration? That’s a little more complicated, and it fueled a good discussion with...
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Filed under: Industry Insights, SoC, verification, IP, Atrenta, Arasan Chip Systems, DesignCon, Virage Logic
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Tech Tip: Easy Way To Re-Run Using The Same Seed
By Team Specman
on February 5, 2010
[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week’s guest blogger] Often we want to re-run a simulation with the exact same random seed that was used in the previous one. Unfortunately far too many people (ok, maybe...
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Filed under: Specman, IES-XL, Funcional Verification
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What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!
By Gerald "Jerry" Grzenia
on February 4, 2010
Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has been a often requested feature and is particularly important for our mil-aero customers. The DEHDL environment has conventionally provided support for vector fonts...
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Filed under: PCB design, DEHDL, Allegroro, SPB 16.3, File Directives, Design Entry
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Apple A4: What We’ve Heard, What We Can Learn
By Richard Goering
on February 3, 2010
The big mystery behind the recent Apple iPad announcement is the A4 processor that powers this touchscreen, “tablet” PC. What’s in it, and why did Apple design its own system-on-chip (SoC) as opposed to using off-the-shelf hardware?...
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Filed under: Industry Insights, SoC, Apple, A4, iPad
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What Can We Learn From The iPad About Chip Design?
By Jack Erickson
on February 2, 2010
You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT...
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Filed under: Logic Design, ARM, system design, IP, Jack Erickson, Apple, Imagination, software, iPad
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What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology Adoption?
By Steven Brown
on February 2, 2010
Cadence is in the vanguard of a movement to a higher level of productivity via the abstraction and automation provided by Transaction Level Modeling (TLM). The industry is motivated to adopt this new methodology by its promise of achieving profitable...
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Filed under: System Design and Verification, verification, IP re-use, RTL, TLM, synthesis
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Three Reasons to Move to EDI System 9.1
By Robert Dwyer
on February 1, 2010
We recently announced the 9.1 version of the Encounter Digital Implementation System. Head over to http://downloads.cadence.com , select your platform and choose EDI91. Notice that in our download system, we’re calling it EDI as opposed to the former...
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Filed under: Digital Implementation, Encounter Digital Implementation System 9.1, EDI system Encounter Digital Implementation System, Foundation Flow Design Closure
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Intel Speaker: How to Avoid “Firefighting” in Verification
By Richard Goering
on February 1, 2010
Can verification engineers gain control over the verification process, and stop being full-time firefighters? With proper planning, communication, and organization, the answer is “yes,” according to Allison Goodman, validation program manager...
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Comments (1)
Filed under: Industry Insights, Intel, verification, Incisive, DVClub
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