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Highlights From ClubT Hertzelia
By Team Specman
on November 19, 2009
Over 125 Verification engineers honored us this past Tuesday by attending the annual "ClubT" in Hertzelia. Here are some of the highlights (and if you were an attendee please post your feedback or follow-up questions in the comments below):...
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Filed under: Functional Verification, e, Specman, IES-XL, ClubT
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User Interview: How ECO Handling Works With Equivalence Checking
By Richard Goering
on November 19, 2009
Vishvabhusan Pati is a senior staff engineer and manager at Qualcomm , where he’s involved in design work and formal and semi-formal design verification. In this Q&A interview, he discusses advantages and limitations of formal equivalence checking...
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Filed under: Industry Insights, Qualcomm, Encounter, Conformal, ECO
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Observations From This Autumn's Events
By Joseph Hupcey III
on November 18, 2009
As you may recall I was involved in producing several events this past fall . Allow me to share a few nuggets from the experience: Specialization Is Accelerating As industries advance, there is always a natural trend toward increasing specialization since...
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Filed under: Functional Verification, CDNLive, AMS, Specman, IES-XL, Twitter, ESL, Trailblazer, ClubT
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Guest Blog: Characterizing Process Variability At 32 nm And Below
By Richard Goering
on November 18, 2009
Process characterization becomes much more complex as feature sizes shrink. In this guest blog Jim Bordelon, president and CTO of Stratosphere Solutions , describes requirements and methodologies for modeling variability at 32 nm and below. Peering under...
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Filed under: Industry Insights, IBM, Stratosphere Solutions, CMOS, 32nm
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What's Good About the SPB16.3 Release? Join The Virtual Conference 12/02/09 and See!
By Gerald "Jerry" Grzenia
on November 17, 2009
You will NOT want to miss this event! The first ever Virtual Trade Show for the SPB products will take place on December 2, 2009. Mark your calendars and register ASAP! The event opens at 11:00am EST. All the Cadence® SPB16.3 products will be covered...
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Filed under: PCB design, OrCAD, Allegroro, IC Packaging and SiP Design, PCB, Virtual Conference, SPB 16.3
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Things You Didn't Know About The Rhinovirus and ViVA (Part 3)
By Stacy Whiteman
on November 17, 2009
Okay, so I really have no idea how to tie those 2 things together, but I ran across this little widget the other day and just had to share it (slide the slider until it's about 2/3 of the way across). I know we've all seen electron microscope...
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Filed under: Custom IC Design, Virtuoso, Virtuoso IC 6.1.3, ViVa-XL, Virtuoso Analog Design Environment, IC 6.1
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User Panel: Can Formal Tools Reduce Need For Simulation?
By Richard Goering
on November 16, 2009
It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort...
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Filed under: Industry Insights, Conformal, Logic Design, Formal, ECO
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Interview With Teradyne on Metric Driven Verification
By Team MDV
on November 13, 2009
Welcome to the first TeamMDV blog. We are excited to bring you information, tips, tricks and recommendations all centered around Metric Driven Verification (MDV). To start, here is an interview with Dylan Dobbyn, the verification manager at Teradyne,...
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Filed under: Functional Verification, Enterprise Manager, SoC, IES, Enterprise Planner, Incisive, MDV
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Android System Verification Part 2
By Jason Andrews
on November 13, 2009
In Part 1 of this series on Android System Verification I provided the basics about how to run the Android emulator. When I initially looked at the emulator I was looking for information about available verification techniques, primarily at the system...
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Filed under: System Design and Verification, ISX, android, Java, Monkey
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User Interview: Formal Analysis Speeds IP Connectivity Verification
By Richard Goering
on November 12, 2009
The biggest challenge with verification is “always the schedule,” according to Chaitanya Kosaraju, senior design engineer at Xilinx . Thus, anything that can cut verification time without compromising coverage presents a huge advantage. At...
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Filed under: Industry Insights, IFV, Xilinx, CDNLive!, RTLL Compiler, Formalmal, Incisive Formal Verifier
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