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Blogs

Electromigration – What IC Designers Need to Know

If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in...  Read More »
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IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

Winning in the IoT applications space requires a system-level design mentality and an abiding insight into energy, cost and time-to-market challenges....  Read More »
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Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC Packaging Tools

Normal 0 false false false EN-US X-NONE X-NONE Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the...  Read More »
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What's Good About Allegro Design Workbench Team Collaboration? Find Out in the 16.6 Release

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration: Logical design integrator Responsible for front-end design Physical design integrator Responsible for back-end design A logical...  Read More »
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Whiteboard Wednesdays - USB Controller Connectivity

In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC) and how they improve connectivity...  Read More »
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Challenges and Applications in a 3D World

Confronting the challenges and possibilities of 3D silicon design starts with comprehensive simulation and verification models....  Read More »
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IBM Lithography Expert: Making 10nm IC Design Possible

Development work is underway on the 10nm process node - but can we get there with conventional lithography? In a recorded presentation available at the Cadence web site, Lars Liebmann, distinguished engineer at IBM, says yes - but he notes that it will...  Read More »
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Flash Memory Summit: Marveling at IBM’s Staying Power

SANTA CLARA, Calif.—Sometimes in this mile-a-minute business of ours, you have to sit back and reflect. Today, I'm thinking about 103-year-old IBM. Most technology companies have a relatively short half-life, and few companies in general last...  Read More »
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Whiteboard Wednesdays - Verification Made Easy with Memory Models

In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help...  Read More »
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New Technical Resources for Encounter Test Users on http://support.cadence.com

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to...  Read More »
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