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Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
By Richard Goering
on May 21, 2012
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries... Read more »
Filed under: Industry Insights, Si2, SiP, Standards, stacked die, 3D, TSV, GSA, 3D IC, 3D-IC, wide i/o, foundry, Potts, 2.5D, wide io, GSA 3D IC, via, OSAT, thernal, power density, Ken Potts
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Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
By Richard Goering
on May 17, 2012
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new... Read more »
Filed under: Industry Insights, 3D ICs, SoC, Semico, IP, Kapoor, IP quality, system on chip, PCI Express, semiconductor IP, PCIe, silicon IP, 3D-ICs, NVM Express, NVMe, IP subsystems, system-driven IP, Impact, Feldhan, IP ecosystem, design factory
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Measuring 2-Tone Intermodulation Using Envelope-Following Analysis
By Tawna Wilsey
on May 16, 2012
From time to time, SpectreRF users simulate very large, extracted-view circuits in 2+ tone QPSS. In many of those cases, memory requirements exceed the available resources. When that happens and small-signal approximations aren’t applicable, the... Read more »
Filed under: RF design, RF Block Simulation, wireless integrated circuit verification, RF designer, Virtuoso Spectre Simulator GXL, Spectre, Spectre RF, Harmonic Balance, spectreRF, RFIC, MMSIM, RF Simulation, Analog Simulation, ADE, RF, RF spectre spectreRF, envelope, simulation, fast envelope, spectre spectreRF, analog, HB, analog/RF, SpectreRF tutorials
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A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
By Parag Bhatnagar
on May 16, 2012
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else... Read more »
Filed under: mixed-signal, ECOs, signoff, mixed signal, OpenAccess, Virtuoso, Encounter, IC 6.1, mixed signal design, STA, timing model, static timing analysis, oa, ECO, open access, Mixed signal physical implementation, mixed-signal ECOs, parasitic, Virtuoso environment, mixed signal solution, EDI, EDIS, mixed signal implementation, ECOs and PCells
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How Debug Breakthroughs are Enabled by In-Circuit Acceleration
By Frank Schirrmeister
on May 16, 2012
We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit... Read more »
Filed under: Acceleration, Emulation, Incisive, functional verification, DAC, System Design and Verification, CDNLive, debug, System Development Suite, Palladium XP, Design Automation Conference, in-circuit emulation, In-circuit acceleration, AMD, DAC breakfast
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What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on May 15, 2012
The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow . These flows provide the benefit of both a guided flow and the simplicity of a default flow. The 2 Point Flow: Provides the benefits of a default flow -... Read more »
Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, GRE, global route, design, routing, High Speed, SPB16.5, Allegro 16.5, bundle compression, disabiling bundle compression, interconnects, 2 point flow
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