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See Cadence IP Up Close at the TSMC Symposiums
By Paula Jones on April 16, 2014
Want to see what Cadence has been up to recently in IP? Register for the upcoming TSMC 2014 Technology Symposiums. You'll find Cadence in Booth #613 at the San Jose event on Tuesday, April 22. We'll also be at the Boston TSMC Symposium on April... Read more »
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Learn Logic built-in self-test (LBIST) macro generation and insertion at your desk
By Sumeet Aggarwal on April 16, 2014
Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.... Read more »
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Keynote: EDA “MOOC” Opens Door to a Planet of Talent
By Richard Goering on April 16, 2014
Participants at the recent CCC/SIGDA Workshop on Extreme Scale Design Automation discussed various ways to motivate students to consider EDA-related careers. And few approaches have cast a broader net than an EDA-related Massive Open Online Course taught... Read more »
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Multi-Fabric Planning for Smarter Design: Q&A with Kevin Rinebold
By Brian Fuller on April 15, 2014
Manage chip, pc-board and IC package design interdependencies better with multi-fabric planning, says Cadence senior product marketing manager Kevin Rinebold. ... Read more »
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Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support
By Stacy Whiteman on April 15, 2014
Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL. Application Notes 1. Physical Verification Checks and Generic... Read more »
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What's Good About Capture’s Auto Part Reference? 16.6 has a Few New Enhancements!
By Gerald "Jerry" Grzenia on April 15, 2014
The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic. Read on for more details … Design Level Auto-Reference Designator Assignments In... Read more »
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