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How Debug Breakthroughs are Enabled by In-Circuit Acceleration
By Frank Schirrmeister
on May 16, 2012
We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit... Read more »
Filed under: Acceleration, Emulation, Incisive, functional verification, DAC, System Design and Verification, CDNLive, debug, System Development Suite, Palladium XP, Design Automation Conference, in-circuit emulation, In-circuit acceleration, AMD, DAC breakfast
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What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on May 15, 2012
The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow . These flows provide the benefit of both a guided flow and the simplicity of a default flow. The 2 Point Flow: Provides the benefits of a default flow -... Read more »
Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, GRE, global route, design, routing, High Speed, SPB16.5, Allegro 16.5, bundle compression, disabiling bundle compression, interconnects, 2 point flow
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The Facts: Why Accelerated VIP Is Needed for SoC Verification
By Peter Heller
on May 15, 2012
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already... Read more »
Filed under: Functional Verification, SystemVerilog, SystemC, VIP, verification, uvm, Palladium XP, simulation, e language, Palladium, verification IP, ACE verification, AVIP, acceleration, simulation VIP, SCE-MI, VIP Catalog, Accelerated VIP, emulation, protocol verification
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How IP Subsystem Will Speed NVM Express (NVMe) Adoption
By Richard Goering
on May 15, 2012
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together... Read more »
Filed under: Industry Insights, VIP, memory, storage, SoC Integration, PCI Express, NAND flash, PCIe, firmware, SSDs, NVM Express, SATA, NVMe, verificationi IP, solid state drives, IP subsystem, non-volatile memory, NVMe controller
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In-Circuit Acceleration – A New IC Verification Use Model
By Richard Goering
on May 15, 2012
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification... Read more »
Filed under: Industry Insights, Palladium, SystemC, virtual platforms, verification, Incisive, Verification IP, VIP, acceleration, emulator, multi-core, debugging, ICE, in-circuit emulation, System Development Suite, FPGA prototyping, Virtual System Platform, Verification Computing Platform, Palladium XP, RTL simulation, IC verification, software deveopment, AVIP, development platform, rapid prototoyping, in-circuit acceleration, accelerated VIP, virtuaul prototypes, simulation acceleration
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Adding Custom Shapes and Text is New and Improved in EDI System 11
By Brian Wallace
on May 14, 2012
You may have noticed that in the Encounter Digital Implementation (EDI) System 11 the commands addCustomBox, addCustomLine and addCustomText are no longer in the documentation. These previous commands weren't cutting it when it came to the features... Read more »
Filed under: dbGet, Encounter Digital Implementation, EDI 11, EDI 11.1, digital implementation, OpenAccess, custom shapes, add_shape, custom text, add_text
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