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Whiteboard Wednesdays - Verification Made Easy with Memory Models
By Corrie Callenbach on August 19, 2014
In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help... Read more »
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New Technical Resources for Encounter Test Users on http://support.cadence.com
By Mukesh on August 19, 2014
Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to... Read more »
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Highlights from Recent IEEE 802.3 Ethernet Standards Meeting
By Arthur Marris on August 18, 2014
I wanted to share with you a number of updates from last month's IEEE 802.3 meeting in San Diego, California. Cadence has a comprehensive portfolio of design and verification IP, many of which support the latest Ethernet standards. Here are my observations... Read more »
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3D-IC Working Group—Tool Support Needed, But “Gaps” May Be Narrowing
By Richard Goering on August 17, 2014
Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and methodologies, according to presenters at a recent meeting... Read more »
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DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
By Team Allegro on August 14, 2014
The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied... Read more »
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Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
By Chinmay Banerjee on August 13, 2014
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance... Read more »
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