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Cadence EDA360 Theater – Customers, Partners Speak Out at DAC 2012
By Richard Goering
on May 29, 2012
Sometimes it's best to let other people do the talking. That's the approach Cadence has taken this year at the Design Automation Conference ( DAC 2012 ) at the EDA360 Theater at the Cadence booth (#1930). This theater will feature three days of... Read more »
Filed under: Industry Insights, ARM, DAC, AMD, broadcom, stmicroelectronics, Xilinx, GlobalFoundries, Fujitsu, TSMC, Cadence, Samsung, Duolog, Design Automation Conference, EDA360 Theater, LSI, Oski, DAC 2012, Dini Group, TowerJazz, customers, Maxim, partners, SMIC, LeCroy
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12 Hot EDA Topics – 78 DAC Demo Sessions
By Richard Goering
on May 24, 2012
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running... Read more »
Filed under: Industry Insights, ARM, DAC, low power, Analog, verification, IP, Mixed-Signal, mixed signal, ECO, VIP, custom, system level, 20nm, 3D IC, 3D-IC, signoff, DAC 2012, product demos, DAC demo suites, demo suites, Cadence demos
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Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
By Jason Andrews
on May 24, 2012
There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical... Read more »
Filed under: embedded software, QEMU, linux, SystemC, System Design and Verification, virtual platforms, virtual prototypes, Virtual System Platform, Xilinx, Zync-7000, USB, physical USB devices
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Get Started on UVM-e with Free Introductory Video Tutorials
By Team Specman
on May 24, 2012
One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos... Read more »
Filed under: Functional Verification, Testbench simulation, Verification methodology , OVM, SoC, eRM, CDV, SystemVerilog, IES, e, Specman, IEEE 1647, hvl, verification, Incisive, MDV, VMM, Vera, uvm, testbench, simulation, coverage, videos, universal verification methodology, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, Questa, VCS, IUS, UVM tutorial, verification tutorial, AVM, video tutorial, URM, cowbell, UVM-e, UVMe
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DAC 2012: “IP Talks!” Reveals Latest in Semiconductor IP
By Richard Goering
on May 24, 2012
If you want to know what's new in the world of semiconductor intellectual property (IP), the place to be is at the IP Talks! presentations at the Cadence ChipEstimate.com booth at the Design Automation Conference ( DAC 2012 ) June 4-6. Over this three... Read more »
Filed under: Industry Insights, ARM, DAC, SoC, IP, ChipEstimate, Cadence, system on chip, John Heinlein, IP Talks!, semiconductor IP, DAC2012, IP Talks
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Modeling Oscillators with Arbitrary Phase Noise Profiles
By Tawna Wilsey
on May 24, 2012
When you need to include noisy oscillators in SpectreRF transceiver simulations, you have at least 3 options: 1) Semi-autonomous simulation is the most accurate approach, recommended whenever the transistor-level model of the oscillator is available.... Read more »
Filed under: RF design, Virtuoso Spectre, Virtuoso Spectre Simulator GXL, Spectre, Spectre RF, Harmonic Balance, RFIC, VCO, MMSIM, Circuit simulation, RF Simulation, Analog Simulation, ADE, RF, APS, simulation, Oscillator, phase noise, analog, HB, analog/RF, PNoise, HBnoise, noise profiles
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