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	createPGPin to the rescue: getting the power pins you want in your block LEF By Kari Summers on October 10, 2008 Hi Everyone! Welcome to my first blog post! My plan for this space is to share with you various tips and tricks in SoC-Encounter as well as new things I learn along the way. I use Encounter every day as part of my job in Cadence Design Services. Knowledge... Read more » Comments (0) Filed under: SoC-Encounter, LEF, createPGPin, lefOut followpins

	Going broadside with electromagnetic modeling of advanced processes By Thomas Costas on October 09, 2008 It has caught my attention that designs using fabrication processes such as 65nm, 45nm, 32nm, and smaller, have changed the landscape when it comes to electromagnetic (EM) modeling of components and interconnects. These designs have to contend with the... Read more » Comments (0) Filed under: RF design, Circuit design, Electromagnetic analysis, wireless integrated circuit verification, Electromagnetic (EM), Virtuoso RF Designer

	Chip Planning at Blazing Speeds with Incyte! By Kenneth Chang on October 09, 2008 I'm sooo pumped up about this new chip planning tool we acquired 6 months ago. Out of all the Cadence tools, this is definitely one of the hottest stuff according to customer feedback - it has the potential to change the way ASIC engineers and managers... Read more » Comments (0) Filed under: Logic Design, incyte, chip planning, speed

	What's Good about the new "Class" Scope for Match Groups in Constraint Manager? By Gerald "Jerry" Grzenia on October 08, 2008 In the SPB16.01 release, for the Constraint Manager in DEHDL, the is a new scope of "Class" for Match Groups. This new scope will utilize the “Net Class” signal grouping introduced in 16.0, and allow users to mimic the capability... Read more » Comments (0) Filed under: PCB design, Class Scope, Constraint Manager

	System-level design and verification - at the center! By Ran Avinun on October 07, 2008 This year, Cadence increases its focus on system-level design and verification events. During the latest CDNLive San-Jose that was held in September, the guest keynote - Dr. Jan Rabaey, Distinguished Professor of Electrical Engineering at the University... Read more » Comments (0) Filed under: System simulation and analysis, System Design and Verification, Acceleration, Emulation, Hardware/software co-verification, ESL handoff, ISX, CDNLive! Silicon Valley 2008, Coverage Driven Verification for Embedded Software, ESL, embedded SW engineer, architect, embedded software

	Does Cadence filter my blogs? Why Blog? By Kenneth Chang on October 07, 2008 I debated on blogging on this site - debated for over a month. I was already doing something similar elsewhere, so why do it here? In my postings outside of Cadence, I did it because it was vendor-neutral, and I could speak my mind like an artist with... Read more » Comments (1) Filed under: Logic Design, blog

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