Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Community

Visit the User forums »
There are 265 guest(s) and 0 member(s) online:


 
Archived Webinar – An Introduction to High-Level Synthesis (HLS)
By Richard Goering on July 28, 2014
High-level synthesis (HLS) is rapidly entering the IC design mainstream - but how much do you know about this emerging technology? A recently archived Cadence webinar sets the record straight about what HLS is (and is not), how it works, who's using... Read more »
Comments (0)
 
Filed under: , , , , , ,
 

 
What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6 Has It!
By Gerald "Jerry" Grzenia on July 28, 2014
Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive... Read more »
Comments (0)
 
Filed under: , , , , ,
 

 
DAC 2014 Panel: Chip, Package, and Board Design Must be Reconsidered
By Brian Fuller on July 24, 2014
High-speed cross fabric interface design requires an understanding that digital is more analog and that chip, package and board design must be reconsidered, according to a DAC 2014 panel of experts.... Read more »
Comments (0)
 
Filed under: , , , , , , ,
 

 
Boosting Design Productivity with Team Design and PTC Windchill: Webinar
By Brian Fuller on July 23, 2014
The electronics industry has recognized the need for structured design methodologies that integrate ECAD design with Product Data Management (PDM) systems. Allegro's Team Design cockpit now integrates with PTC Windchill's PDM solution. ... Read more »
Comments (0)
 
Filed under: , , , , , , ,
 

 
Designer View – Getting the Best Use From Static Low-Power Verification
By Richard Goering on July 23, 2014
Do you want assurance that your system-on-chip (SoC) netlists are "power clean?" In a recorded presentation on the Cadence web site, Harshat Pant, principal engineer at Broadcom, shows how static low-power verification can provide that assurance... Read more »
Comments (0)
 
Filed under: , , , , ,
 

 
Whiteboard Wednesdays - Get to Know 802.11a/c Wireless Analog Front End Solution
By Corrie Callenbach on July 22, 2014
In this week's Whiteboard Wednesdays, Priyank Shukla discusses Cadence's wireless analog front end (AFE) solution for 802.11a/c.... Read more »
Comments (0)
 
Filed under: , , , ,
 

 
View all blog posts »


Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.