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	Built-in Message Logging – Part 1 of 2 By Team Specman on March 11, 2010 [Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK] Messaging is important for two main reasons: It is essential for debugging It can greatly impact simulation performance This is why Specman has a messaging infrastructure... Read more » Comments (0) Filed under: Functional Verification, e, Specman, AOP, IES-XL, tech tips

	What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release! By Gerald "Jerry" Grzenia on March 10, 2010 You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release These enhancements will improve your experience with analyzing simulation results especially for dense designs. These features include: Easy to... Read more » Comments (0) Filed under: PCB design, Allegro, AMS simulator, SPB 16.3, AMS

	Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient By Michael Jacobs on March 10, 2010 Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to... Read more » Comments (0) Filed under: Digital Implementation, Signoff Analysis, static timing analysis, Early Rail Analysis, dynamic rail analysis, power analysis, SI analysis, signal integrity, noise analysis, timing system, Multi-Core and Parallel rocessing, timing convergence, Timing Constraints, Timing analysis, Extraction, OCV, Statistical, signoff

	Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements By Stacy Whiteman on March 10, 2010 I'm not going to beat around the bush here. I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4. I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that... Read more » Comments (2) Filed under: Custom IC Design, Virtuoso, IC 6.1.4, Virtuoso Analog Design Environment

	Challenging Misconceptions About Verification Languages By Richard Goering on March 10, 2010 One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way... Read more » Comments (2) Filed under: Industry Insights, DVCon, SystemC, OVM, verification, e, OOP, HVL

	VIP Portfolio Extension: New AMBA 4 Protocol Support By Team Specman on March 08, 2010 ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol. Here is the official announcement, which... Read more » Comments (0) Filed under: Functional Verification, OVM, metric driven verification (MDV), ARM, VIP, Cadence VIP portfolio, vPlan, AMBA, CMS, Compliance Management System

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