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Electromigration – What IC Designers Need to Know
By Richard Goering on September 01, 2014
If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in... Read more »
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IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT
By Seow Yin Lim on August 28, 2014
Winning in the IoT applications space requires a system-level design mentality and an abiding insight into energy, cost and time-to-market challenges.... Read more »
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Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC Packaging Tools
By Jeffrey Gallagher on August 28, 2014
Normal 0 false false false EN-US X-NONE X-NONE Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the... Read more »
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What's Good About Allegro Design Workbench Team Collaboration? Find Out in the 16.6 Release
By Gerald "Jerry" Grzenia on August 27, 2014
The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration: Logical design integrator Responsible for front-end design Physical design integrator Responsible for back-end design A logical... Read more »
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Whiteboard Wednesdays - USB Controller Connectivity
By Corrie Callenbach on August 26, 2014
In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC) and how they improve connectivity... Read more »
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Challenges and Applications in a 3D World
By Scott Jacobson on August 26, 2014
Confronting the challenges and possibilities of 3D silicon design starts with comprehensive simulation and verification models.... Read more »
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