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Calypto CEO Interview: Why System Realization Needs Sequential Analysis
By Richard Goering
on September 02, 2010
One important enabling technology of a transaction-level modeling (TLM) based design flow is an ability to verify the results of high-level synthesis. Calypto Design Systems , a member of the recently-formed Cadence System Realization Alliance , is playing... Read more »
Filed under: DAC, High-level Synthesis, HLS, verification, C-to-Silicon, Formal, Industry Insights: ARM, EDA360, Sandoval, sequential, Calypto, analysis
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Join Us at FMCAD October 20-23
By Team Verify
on September 01, 2010
Are you deeply interested in formal and assertion-based verification technology? Are you wondering what algorithms and methodologies are coming over the horizon in this rapidly evolving space? Have you been looking for an opportunity to influence the... Read more »
Filed under: Functional Verification, Formal Analysis, ABV, IEV, formal, IFV, Alok Jain, FMCAD
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What's Good About AMS Simulator New Design Templates? They’re in the SPB16.3 Release!
By Gerald "Jerry" Grzenia
on September 01, 2010
What's Good About AMS Simulator New Design Templates? They're in the SPB16.3 Release!What's Good About AMS Simulator New Design Templates? They're in the SPB16.3 Release!What's Good About AMS Simulator New Design Templates? They're... Read more »
Filed under: AMS simulation, Schematic, AMS simulator, SPB 16.3, Design Entry, AMS, pspice, SPB16.3
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User Interview: Verifying IP With Many Configurations
By Richard Goering
on September 01, 2010
As manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe , Raimund Soenning faces some tough challenges. He's responsible for the design and verification of complex graphics controller SoCs for automotive... Read more »
Filed under: Industry Insights, SoC, specman, verification, IP, Incisive, e, constrained-random, Fujitsu, test generation, Soenning
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All I Really Need to Know About MDV I Learned From Hollywood - Part 2
By Tom Anderson
on September 01, 2010
My last blog entry began a series using quotes from Hollywood movies to illustrate some of the key concepts about metric-driven verification (MDV). Given that this idea was inspired by a rather strange dream, I'm pleased to report that the feedback... Read more »
Filed under: Verification IP modeling, MDV, vPlan, metric-driven verification, verification planning
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ARM, Cadence Webinar: How SOI Impacts Timing and Signal Integrity
By Richard Goering
on August 30, 2010
You probably know that silicon-on-insulator (SOI) technology offers lower power and/or better performance than bulk CMOS, and that qualified IP libraries are available. But what's the impact on the digital design flow? Fairly minimal, but there are... Read more »
Filed under: Industry Insights, ARM, Encounter, IP, SOI, silicon-on-insulator, timing, signal integrity, webinar, noise, SI, history effect
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