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射频设计 

47 resources found
 
Title Type Rated
Cadence QRC Extraction Datasheet
Format: .PDF    Date: 16 Feb 2012
 		Datasheet
 6
Recommend!
Virtuoso Digital Implementation Datasheet
Format: .PDF    Date: 07 Feb 2012
 		Datasheet
 35
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Virtuoso Multi-Mode Simulation Datasheet
Format: .PDF (1MB)    Date: 18 Nov 2011
 		Datasheet
 54
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Verification Solutions for Digitally Calibrated Analog Design
Format: .PDF (1.5MB)    Date: 20 Sep 2011
 		Conference Paper
 0
Recommend!
Mixed-Signal Assertion Based Verification
Format: .PDF    Date: 20 Sep 2011
 		Conference Paper
 1
Recommend!
Archived webinar - Using RF Simulation Technologies for Analog Applications
Date: 24 May 2010
 		Webinar
 2
Recommend!
Assura Physical Verification Datasheet
Format: .PDF    Date: 01 May 2009
 		Datasheet
 21
Recommend!
PCB Design Demo: Implementing RF Circuits on PCBs
Date: 01 Aug 2008
 		Demo
 10
Recommend!
Cadence RF SiP Methodology Kit Overview
Format: .PDF    Date: 01 Jun 2008
 		Datasheet
 2
Recommend!
Virtuoso Passive Component Designer Datasheet
Format: .PDF    Date: 01 Dec 2007
 		Datasheet
 0
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Achieving efficient time to market with Cadence tools
Format: .PDF (5.5MB)    Date: 04 Nov 2007
 		Conference Paper
 2
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eScape to System Verilog: The Surprises
Format: .PDF (1.1MB)    Date: 17 Oct 2007
 		Conference Paper
 0
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The Evolution of RF CMOS, from On-Chip Inductors to Software-Defined Radio SOCs
Format: .PDF (3.7MB)    Date: 17 Oct 2007
 		Conference Paper
 0
Recommend!
Using Parasitic-Aware Simulation in the Design and Verification of Complex RF SiP Modules White Paper
Format: .PDF    Date: 01 Oct 2007
 		White Paper
 3
Recommend!
A Verification Methodology for SoC-Controlled, Highly-Integrated, Mixed-Signal and RF ICs
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 1
Recommend!
Modeling Semi-Ideal External Components Co-Simulation
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
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Capturing Today's Designs using Allegro System Architect
Format: .PDF (3.3MB)    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Correlating and Simulating RLCk and Substrate Parasitics in RF IC Circuit Design
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation White Paper
Format: .PDF    Date: 01 Sep 2007
 		White Paper
 0
Recommend!
Interview: New SoC Functional Verification Kit Kicks it up a Notch
Format: .PDF    Date: 30 Aug 2007
 		Cadence Article
 1
Recommend!
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