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射频设计 

Press Releases
TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design
Cadence Virtuoso IC 6.1 Successfully Deployed by Matsushita for Analog and Mixed-Signal SoC Designs
Renesas Adopts Cadence Virtuoso Spectre Circuit Simulator with Turbo Technology

Articles
Heard at DAC: the Question on Everyone’s Mind
EDA360: My Modest Opinion
Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform

Events
CDNLive Silicon Valley 2015
03/10/2015 - San Jose
CDNLive EMEA 2015
04/27/2015 - Munich

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