Cadence Allegro and OrCAD 16.3 was our major release for 2009 and incorporates significant updates to our OrCAD and Allegro PCB flows, Allegro Design Workbench for library and design data management and our IC Packaging and SiP co-design solutions. It is focused on addressing 4 key technology challenges areas that are driven by customers macro-level business goals, managing miniaturization and design complexity, managing the design life cycle, managing faster data throughput and finally managing environmental concerns. Each product area has a “What’s New” tab that provides details on what is “new” for this latest release.
What’s New in IC Packaging & SiP 16.5 Release
Physical Layout and Co-Design
- Cadence APD and SiP – All tiers
- Wirebonding improvements
- BGA footprint report (Excel)
- Embedded component support
- Usability improvements
- Highlighting, pin/finger selection, symbol editor, icons relocated
- Cadence SiP Layout XL or APD licensed with SiP Layout XL
- Route planning with Interconnect Flow Designer
- Assembly rule checking for APD
- 3D Viewer integration enhancements
- Co-Design Options for Cadence SiP Layout XL
- Distributed Co-Design with Virtuoso and Encounter
APSI L and SiP SI XL
- Productivity Enhancements
- Signal Integrity Application Mode
- Setup Advisor / Setup Audit
- Model Editor Usability
- Memory Interface Design
- Improved reporting
- Timing Closure with TimingDesigner
- DDR3 Design-in Kit
- AMI model support enhancements